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1. 发明授权

US07120889B2 Integrated circuit schematics and layouts 有权
标题翻译：集成电路原理图和布局
公开(公告)号：US07120889B2
公开(公告)日：2006-10-10
申请号：US10782246
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Integrated circuit schematics and layouts are provided. A schematic for an integrated circuit includes a number of circuit components interconnected by lines and a number of width markers, each assigned a width marker having a minimum width parameter.
摘要翻译：提供集成电路原理图和布局。集成电路的示意图包括通过线互连的多个电路部件和多个宽度标记，每个分配宽度标记具有最小宽度参数。

2. 发明授权

US07428714B2 Line width error check 失效
标题翻译：行宽错误检查
公开(公告)号：US07428714B2
公开(公告)日：2008-09-23
申请号：US10781959
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F9/45 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum line width, and associating a line width parameter with each line width marker, the line width parameter corresponding to a line width for the marked line. The line width parameters for each line width marker are compared to the actual layout line width.
摘要翻译：一种在集成电路中检查线宽中的误差的方法包括用标记识别具有大于最小线宽的线宽的线，以及将线宽参数与每个线宽标记相关联，线宽度参数对应于标记线的线宽。将每个线宽标记的线宽参数与实际布局线宽进行比较。

3. 发明授权

US07032199B2 Design rule checking integrated circuits 失效
标题翻译：设计规则检查集成电路
公开(公告)号：US07032199B2
公开(公告)日：2006-04-18
申请号：US10781964
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of design rule checking an integrated circuit identifies any line having a line width marker and line width parameter, extracts each line having a line width marker, determines the line width parameter for each extracted line, and compares the line width parameter with an actual line width for the line.
摘要翻译：设计规则检查集成电路的方法识别具有线宽标记和线宽参数的任何线，提取具有线宽标记的每条线，确定每条提取线的线宽参数，并将线宽参数与实际线宽线。

4. 发明授权

US06944839B2 Checking layout accuracy in integrated circuit designs 失效
标题翻译：检查集成电路设计中的布局精度
公开(公告)号：US06944839B2
公开(公告)日：2005-09-13
申请号：US10782247
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for checking layout accuracy in an integrated circuit design includes creating a schematic, adding a line width marker to selected lines having a width greater than an absolute minimum width, and assigning a line width to each line width marker. A layout is created and is checked versus the schematic. A design is extracted from the layout. The design has a design line width corresponding to each line having a line width marker. The design line width is checked versus the marker line width for each line having a line width marker.
摘要翻译：一种用于检查集成电路设计中的布局精度的方法包括创建示意图，将线宽标记添加到具有大于绝对最小宽度的宽度的所选择的线，以及为每个线宽标记分配线宽。创建布局并检查相对于原理图。从布局中提取设计。该设计具有对应于具有线宽标记的每一行的设计线宽度。对于具有线宽标记的每一行，检查设计线宽度与标记线宽度。

5. 发明授权

US06769103B2 Line width check in layout database 失效
公开(公告)号：US06769103B2
公开(公告)日：2004-07-27
申请号：US10199727
申请日：2002-07-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A method for checking the accuracy of non-standard line widths in a layout includes marking lines with a line width marker, and associating the line width markers with the lines throughout a design process to ensure that the lines remain at the desired widths.

6. 发明授权

US07107554B2 Line width check in layout database 有权
标题翻译：线宽检查布局数据库
公开(公告)号：US07107554B2
公开(公告)日：2006-09-12
申请号：US10782252
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A machine-readable medium has a set of machine-readable instructions for causing a computer to perform a method. The method includes checking a layout having a layout line width for at least one line versus a schematic having a schematic line width for the at least one line. Extracting a line width property from the schematic and transferring the line width property to the layout are included in the method, as is checking a design for the at least one line versus the schematic.
摘要翻译：机器可读介质具有用于使计算机执行方法的一组机器可读指令。该方法包括检查具有用于至少一行的布局线宽度的布局相对于具有至少一行的示意线宽度的示意图。从原理图中提取线宽属性并将线宽属性传递到布局包含在方法中，正如检查至少一行与原理图的设计一样。

7. 发明授权

US07055115B2 Line width check in layout database 失效
标题翻译：线宽检查布局数据库
公开(公告)号：US07055115B2
公开(公告)日：2006-05-30
申请号：US10782701
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of performing a design rule check on an integrated circuit includes tagging at least one line in a schematic with a width marker and an associated width parameter, extracting the line width marker and the associated line width parameter, comparing the extracted line width parameter with an actual design width for a design line, and generating an error condition when the actual design line width is less than the line width parameter.
摘要翻译：在集成电路上执行设计规则检查的方法包括使用宽度标记和相关联的宽度参数标记示意图中的至少一条线，提取线宽标记和相关线宽参数，将提取的线宽参数与设计线的实际设计宽度，并且当实际设计线宽小于线宽参数时产生错误条件。

8. 发明授权

US07024643B2 Identifying line width errors in integrated circuit designs 失效
标题翻译：识别集成电路设计中的线宽误差
公开(公告)号：US07024643B2
公开(公告)日：2006-04-04
申请号：US10782450
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of identifying line width errors in an integrated circuit design includes adding a line width marker for each of a plurality of lines on a schematic, each line having a schematic line width, creating a layout from the schematic, the layout containing the line width markers and a plurality of layout widths, checking the layout line widths versus the schematic line widths for the plurality of line width marked lines, creating a design representing the layout, the design having a plurality of design line widths, and checking the design line widths versus the layout line widths for the plurality of line width marked lines.
摘要翻译：在集成电路设计中识别线宽误差的方法包括在原理图上为多个线中的每一行添加线宽标记，每行具有示意线宽度，从原理图创建布局，包含线宽度标记和多个布局宽度，检查布局线宽度与多条线宽标记线的示意线宽度，创建表示布局的设计，设计具有多个设计线宽度，以及检查设计线宽度相对于多个线宽标记线的布局线宽度。

9. 发明授权

US08831671B2 Automated parameter adjustment to compensate self adjusting transmit power and sensitivity level at the node B 有权
标题翻译：自动参数调整，以补偿节点B的自调节发射功率和灵敏度级别
公开(公告)号：US08831671B2
公开(公告)日：2014-09-09
申请号：US13621674
申请日：2012-09-17
申请人： Aziz Gholmieh , Farhad Meshkati , Mehmet Yavuz , Siddharth Mohan , Christophe Chevallier
发明人： Aziz Gholmieh , Farhad Meshkati , Mehmet Yavuz , Siddharth Mohan , Christophe Chevallier
IPC分类号： H04B7/00 , H04W52/24 , H04W52/10 , H04W52/36
CPC分类号： H04W52/10 , H04W52/244 , H04W52/246 , H04W52/367
摘要： A small base node such as a Home Base Node (HNB), or femto cell, may reduce its transmit power in order to prevent co-channel or adjacent channel interference, or to limit its coverage area. Once the power is set, the HNB signal to a served Home User Equipment (HUE) its transmit Common Pilot Channel (CPICH) transmit power for accurate path loss estimation. When this power is outside of the permissible range, the HNB adjusts other parameters (such as Random Access Channel (RACH) constant value) to compensate for the error in signaled CPICH power, and thus compensate in that process the error in determining path loss. Similarly, if the uplink sensitivity is adjusted, to prevent interference, parameters would also be adjusted and signaled to the HUE to reflect the link imbalance.
摘要翻译：诸如家庭基站节点（HNB）或毫微微小区之类的小型基站节点可以降低其发射功率，以防止同信道或相邻信道干扰，或限制其覆盖区域。一旦功率被设置，HNB信号到服务的家庭用户设备（HUE），其发射公共导频信道（CPICH）发送功率用于精确的路径损耗估计。当该功率超出允许范围时，HNB调整其他参数（如随机接入信道（RACH）常数值）来补偿信令CPICH功率中的误差，从而在该过程中补偿确定路径损耗的误差。类似地，如果调整上行链路灵敏度，为了防止干扰，参数也将被调整并发出信号到HUE以反映链路不平衡。

10. 发明授权

US08305796B2 Access signal adjustment circuits and methods for memory cells in a cross-point array 有权
标题翻译：交叉点阵列中存储单元的访问信号调整电路和方法
公开(公告)号：US08305796B2
公开(公告)日：2012-11-06
申请号：US13425247
申请日：2012-03-20
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器直接位于包含数据访问电路的FEOL基板之上。在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

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