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1. 发明授权

US07443323B2 Calibrating a digital-to-analog converter 有权
标题翻译：校准数模转换器
公开(公告)号：US07443323B2
公开(公告)日：2008-10-28
申请号：US11651858
申请日：2007-01-10
申请人： Christian J. Rotchford , Brandt Braswell , Jiangbo Gan , Michael L. Gomez , Gerald P. Miaille , Boris V. Razmyslovitch
发明人： Christian J. Rotchford , Brandt Braswell , Jiangbo Gan , Michael L. Gomez , Gerald P. Miaille , Boris V. Razmyslovitch
IPC分类号： H03M1/10
CPC分类号： H03M1/1047 , H03M1/66
摘要： Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.
摘要翻译：用于校准数模转换器的方法和相应的系统包括选择数模转换器中的第一和第二代码区，其中第一和第二代码区被边界分隔开。此后，将波形序列输入到数模转换器，其中波形序列在边界处具有零偏移。然后调整第一和第二代码区之间的相对补偿值以减小数模转换器的输出中的失真。可以使用波形序列的三次谐波失真的大小来测量输出中的失真。调整相对补偿可以包括将数模转换器的输出转换为数字序列，对数字序列进行滤波，并测量数字序列中的谐波失真。

2. 发明申请

US20080165040A1 Calibrating a digital-to-analog converter 有权
公开(公告)号：US20080165040A1
公开(公告)日：2008-07-10
申请号：US11651858
申请日：2007-01-10
申请人： Christian J. Rotchford , Brandt Braswell , Jiangbo Gan , Michael L. Gomez , Gerald P. Miaille , Boris V. Razmyslovitch
发明人： Christian J. Rotchford , Brandt Braswell , Jiangbo Gan , Michael L. Gomez , Gerald P. Miaille , Boris V. Razmyslovitch
IPC分类号： H03M1/10
CPC分类号： H03M1/1047 , H03M1/66
摘要： Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.

3. 发明授权

US07358743B2 Accumulated current counter and method thereof 有权
标题翻译：累积电流计数器及其方法
公开(公告)号：US07358743B2
公开(公告)日：2008-04-15
申请号：US11380479
申请日：2006-04-27
申请人： Gerald P. Miaille
发明人： Gerald P. Miaille
IPC分类号： G01R31/08 , G01R19/00 , G01N27/416 , H02J7/00
CPC分类号： G01R31/3613
摘要： An accumulated current counter (11) includes a sense resistor (30) configured for being coupled in series between an electronic circuit (13) and a power source (12). The sense resistor is further for use in sensing a voltage (VIN(i)) across the sense resistor as a function of a current (Ibatt) provided via the power source. An incremental counter (16) is coupled to the sense resistor for incrementally counting an amount of current, corresponding to an average value of charge Q, going (i) into or (ii) out of the power source. A register (63) accumulates a representation of the incrementally counted current. In one embodiment, the representation of incrementally counted current corresponds to a remaining power source life in hours and minutes.
摘要翻译：累积电流计数器（11）包括被配置为串联耦合在电子电路（13）和电源（12）之间的检测电阻器（30）。感测电阻器进一步用于感测跨越感测电阻器的电压（V IN（i）），作为通过电源提供的电流（Ibatt）的函数。增量计数器（16）耦合到感测电阻器，用于对与电源的平均值（i）进入（i）进入或（ii）电源的电流量进行递增计数。寄存器（63）累加递增计数电流的表示。在一个实施例中，递增计数电流的表示对应于以小时和分钟为单位的剩余电源寿命。

4. 发明授权

US07379002B1 Methods and apparatus for a multi-mode analog-to-digital converter 有权
标题翻译：多模式模数转换器的方法和装置
公开(公告)号：US07379002B1
公开(公告)日：2008-05-27
申请号：US11639676
申请日：2006-12-15
申请人： Zhou Zhixu , Julian Aschieri , Gerald P. Miaille
发明人： Zhou Zhixu , Julian Aschieri , Gerald P. Miaille
IPC分类号： H03M3/00
CPC分类号： H03M3/392 , H03M3/43 , H03M3/452
摘要： A multi-mode analog-to-digital converter includes a delta-sigma analog-to-digital converter circuit configured to receive the analog input and produce a digital bit-stream associated therewith, the delta-sigma analog-to-digital converter including at least one integrator configured to reset to an initial state in response to a reset signal A digital filter circuit is configured to receive the digital bit-stream and produce two filtered outputs derived from the digital bit-stream. During one mode (e.g., a DC mode) the delta-sigma analog-to-digital converter circuit is configured to receive the reset signal and produce the digital bit-stream for a predetermined number of clock cycles, and the digital output corresponds to the first filtered output. In another mode (e.g., an AC mode), the delta-sigma analog-to-digital converter is configured to continuously produce the bit-stream, and the digital output corresponds to the second filtered output.
摘要翻译：多模式模数转换器包括被配置为接收模拟输入并产生与其相关联的数字比特流的Δ-Σ模数转换器电路，该Δ-Σ模数转换器包括在至少一个积分器被配置为响应于复位信号而复位到初始状态。数字滤波器电路被配置为接收数字比特流并产生从数字比特流导出的两个滤波的输出。在一种模式（例如，DC模式）期间，Δ-Σ模数转换器电路被配置为接收复位信号并产生预定数量的时钟周期的数字位流，并且数字输出对应于首先滤波输出。在另一模式（例如，AC模式）中，Δ-Σ模数转换器被配置为连续产生比特流，并且数字输出对应于第二滤波输出。

5. 发明申请

US20090051423A1 DIGITAL AUDIO AMPLIFIERS, ELECTRONIC SYSTEMS, AND METHODS 有权
标题翻译：数字音频放大器，电子系统和方法
公开(公告)号：US20090051423A1
公开(公告)日：2009-02-26
申请号：US11845035
申请日：2007-08-25
申请人： Gerald P. Miaille , Julian Aschieri , Zhou Zhixu
发明人： Gerald P. Miaille , Julian Aschieri , Zhou Zhixu
IPC分类号： H03F3/38
CPC分类号： H03F1/0277 , H03F3/217 , H03F3/3022 , H03F3/72 , H03F2200/03 , H03F2200/432 , H03F2203/7236
摘要： An embodiment of an electronic system includes a digital audio amplifier having a continuous time modulator adapted to generate a difference signal between an audio bitstream and a feedback signal, and to perform a modulation process on the difference signal to generate an input pulse modulated signal, a class D output stage adapted to receive, quantize, and amplify the input pulse modulated signal to generate an output pulse modulated signal, and a feedback path adapted to provide the output pulse modulated signal as the feedback signal to the continuous time modulator. Another embodiment includes a class AB output stage adapted to receive and amplify an input digital audio signal to generate an analog output signal, and circuitry adapted to enable the digital audio amplifier to be configured to enable the class AB output stage and to disable the class D output stage.
摘要翻译：电子系统的一个实施例包括具有连续时间调制器的数字音频放大器，其适于在音频比特流和反馈信号之间产生差分信号，并且对差分信号执行调制处理以产生输入脉冲调制信号， D类输出级适于接收，量化和放大输入脉冲调制信号以产生输出脉冲调制信号，以及适于将输出脉冲调制信号作为反馈信号提供给连续时间调制器的反馈路径。另一个实施例包括AB类输出级，其适于接收和放大输入数字音频信号以产生模拟输出信号，以及适于使数字音频放大器能够被配置为启用AB类输出级并禁用D类的电路输出阶段。

6. 发明授权

US07579908B2 Digital audio amplifiers, electronic systems, and methods 有权
标题翻译：数字音频放大器，电子系统和方法
公开(公告)号：US07579908B2
公开(公告)日：2009-08-25
申请号：US11845035
申请日：2007-08-25
申请人： Gerald P. Miaille , Julian Aschieri , Zhou Zhixu
发明人： Gerald P. Miaille , Julian Aschieri , Zhou Zhixu
IPC分类号： H03F3/38
CPC分类号： H03F1/0277 , H03F3/217 , H03F3/3022 , H03F3/72 , H03F2200/03 , H03F2200/432 , H03F2203/7236
摘要： An embodiment of an electronic system includes a digital audio amplifier having a continuous time modulator adapted to generate a difference signal between an audio bitstream and a feedback signal, and to perform a modulation process on the difference signal to generate an input pulse modulated signal, a class D output stage adapted to receive, quantize, and amplify the input pulse modulated signal to generate an output pulse modulated signal, and a feedback path adapted to provide the output pulse modulated signal as the feedback signal to the continuous time modulator. Another embodiment includes a class AB output stage adapted to receive and amplify an input digital audio signal to generate an analog output signal, and circuitry adapted to enable the digital audio amplifier to be configured to enable the class AB output stage and to disable the class D output stage.
摘要翻译：电子系统的一个实施例包括具有连续时间调制器的数字音频放大器，其适于在音频比特流和反馈信号之间产生差分信号，并且对差分信号执行调制处理以产生输入脉冲调制信号， D类输出级适于接收，量化和放大输入脉冲调制信号以产生输出脉冲调制信号，以及适于将输出脉冲调制信号作为反馈信号提供给连续时间调制器的反馈路径。另一个实施例包括AB类输出级，其适于接收和放大输入数字音频信号以产生模拟输出信号，以及适于使数字音频放大器能够被配置为启用AB类输出级并禁用D类的电路输出阶段。

7. 发明申请

US20080143568A1 METHODS AND APPARATUS FOR A MULTI-MODE ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：用于多模式模数转换器的方法和装置
公开(公告)号：US20080143568A1
公开(公告)日：2008-06-19
申请号：US11639676
申请日：2006-12-15
申请人： Zhou Zhixu , Julian Aschieri , Gerald P. Miaille
发明人： Zhou Zhixu , Julian Aschieri , Gerald P. Miaille
IPC分类号： H03M3/00
CPC分类号： H03M3/392 , H03M3/43 , H03M3/452
摘要： A multi-mode analog-to-digital converter includes a delta-sigma analog-to-digital converter circuit configured to receive the analog input and produce a digital bit-stream associated therewith, the delta-sigma analog-to-digital converter including at least one integrator configured to reset to an initial state in response to a reset signal A digital filter circuit is configured to receive the digital bit-stream and produce two filtered outputs derived from the digital bit-stream. During one mode (e.g., a DC mode) the delta-sigma analog-to-digital converter circuit is configured to receive the reset signal and produce the digital bit-stream for a predetermined number of clock cycles, and the digital output corresponds to the first filtered output. In another mode (e.g., an AC mode), the delta-sigma analog-to-digital converter is configured to continuously produce the bit-stream, and the digital output corresponds to the second filtered output.
摘要翻译：多模式模数转换器包括被配置为接收模拟输入并产生与其相关联的数字比特流的Δ-Σ模数转换器电路，该Δ-Σ模数转换器包括在至少一个积分器被配置为响应于复位信号而复位到初始状态。数字滤波器电路被配置为接收数字比特流并产生从数字比特流导出的两个滤波的输出。在一种模式（例如，DC模式）期间，Δ-Σ模数转换器电路被配置为接收复位信号并产生预定数量的时钟周期的数字位流，并且数字输出对应于首先滤波输出。在另一模式（例如，AC模式）中，Δ-Σ模数转换器被配置为连续产生比特流，并且数字输出对应于第二滤波输出。

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