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1. 发明申请

US20050207478A1 Method and device for passing parameters to a rake receiver 有权
标题翻译：将参数传递给耙式接收器的方法和装置
公开(公告)号：US20050207478A1
公开(公告)日：2005-09-22
申请号：US11045651
申请日：2005-01-28
申请人： Christian Drewes , Manfred Zimmermann , Burkhard Becker , Michael Hofstatter , Wolfgang Haas , Thomas Herndl
发明人： Christian Drewes , Manfred Zimmermann , Burkhard Becker , Michael Hofstatter , Wolfgang Haas , Thomas Herndl
IPC分类号： H04B1/707
CPC分类号： H04B1/7117 , H04B2201/70707
摘要： A device and associated method for passing parameters to a finger in a rake receiver are disclosed. The finger is initially operated with a first parameter set which is held in a first memory area (PAR_RAM). To change the parameter set, a second parameter set is loaded into a second memory area (PAR_CHG_RAM1/2), a check is carried out to determine whether a switching condition (SCHED_RAM) is satisfied, and if it is an access for that finger is switched (MUX) from the first memory area (PAR_RAM) to the second memory area.
摘要翻译：公开了一种用于将参数传递到耙式接收器中的手指的装置和相关联的方法。手指最初是以第一个参数集进行操作，该第一参数集保存在第一个存储区（PAR_RAM）中。为了更改参数集，将第二参数集加载到第二存储器区域（PAR_CHG_RAM 1/2）中，执行检查以确定是否满足切换条件（SCHED_RAM），并且如果是该手指的访问被切换（MUX）从第一存储区（PAR_RAM）切换到第二存储区。

2. 发明授权

US07675963B2 Method and device for passing parameters to rake receiver 有权
标题翻译：将参数传递给耙式接收机的方法和装置
公开(公告)号：US07675963B2
公开(公告)日：2010-03-09
申请号：US11045651
申请日：2005-01-28
申请人： Christian Drewes , Manfred Zimmermann , Burkhard Becker , Michael Holstätter , Wolfgang Haas , Thomas Herndl
发明人： Christian Drewes , Manfred Zimmermann , Burkhard Becker , Michael Holstätter , Wolfgang Haas , Thomas Herndl
IPC分类号： H04B1/00
CPC分类号： H04B1/7117 , H04B2201/70707
摘要： A device and associated method for passing parameters to a finger in a rake receiver are disclosed. The finger is initially operated with a first parameter set which is held in a first memory area (PAR_RAM). To change the parameter set, a second parameter set is loaded into a second memory area (PAR_CHG_RAM1/2), a check is carried out to determine whether a switching condition (SCHED_RAM) is satisfied, and if it is an access for that finger is switched (MUX) from the first memory area (PAR_RAM) to the second memory area.
摘要翻译：公开了一种用于将参数传递到耙式接收器中的手指的装置和相关联的方法。手指最初是以第一个参数集进行操作，该第一参数集保存在第一个存储区（PAR_RAM）中。要更改参数集，第二个参数集加载到第二个存储器区域（PAR_CHG_RAM1 / 2）中，执行检查以确定是否满足切换条件（SCHED_RAM），如果是手指的存取（MUX）从第一存储区（PAR_RAM）切换到第二存储区。

3. 发明授权

US07269777B2 Decoding apparatus, trellis processor, and method for operating the decoder 有权
标题翻译：解码装置，网格处理器和操作解码器的方法
公开(公告)号：US07269777B2
公开(公告)日：2007-09-11
申请号：US10799099
申请日：2004-03-12
申请人： Burkhard Becker , Jens Berkmann , Thomas Herndl
发明人： Burkhard Becker , Jens Berkmann , Thomas Herndl
IPC分类号： H03M13/29
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/41 , H03M13/6511 , H03M13/6569
摘要： A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.
摘要翻译：解码装置包括用于turbo解码和维特比解码的至少一个解码器，用于对卷积码进行维特比解码的至少一个第一数据路径，用于turbo码的解码的至少一个第二数据路径，以及具有多个独立存储区域的公共存储器。可以通过Viterbi模式中的第一数据路径和turbo模式中的第二数据路径分配至少一个存储区域。本发明还包括网格处理器和操作解码装置的方法，其中第一数据路径和第二数据路径的至少一部分可以共同用于turbo解码和维特比解码。

4. 发明申请

US20050229075A1 Parallel processing for decoding and cyclic redundancy checking for the reception of mobile radio signals 失效
标题翻译：用于解码和循环冗余校验的并行处理用于接收移动无线电信号
公开(公告)号：US20050229075A1
公开(公告)日：2005-10-13
申请号：US11063949
申请日：2005-02-23
申请人： Jens Berkmann , Wolfgang Haas , Thomas Herndl , Gerald Hodits , Armin Hautle , Sasha Simeunovic
发明人： Jens Berkmann , Wolfgang Haas , Thomas Herndl , Gerald Hodits , Armin Hautle , Sasha Simeunovic
IPC分类号： H03M13/09 , H04L1/00 , H03M13/00
CPC分类号： H04L1/0059 , H03M13/09 , H04L1/0046 , H04L1/0054 , H04L1/0061
摘要： Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.
摘要翻译：取决于解码的有效载荷信号位（一个或多个），冗余校验位（p＆gt; m1＆lt; 通过维特比回溯产生的这些位中的一些位通过分配装置（1）从前面插入到线性反馈移位寄存器（10）中，，或者这些位中的一些位从后部通过分配装置（1）插入到线性反馈移位寄存器（10）中，或者它们全部从后面插入到线性反馈移位寄存器（20）分配的系数不变，或者全部从前面插入到移位寄存器中，分配的系数被反转。这允许在移位寄存器（10; 20）中的发送数据块上执行冗余校验处理，而不会临时存储由解码处理产生的位。

5. 发明授权

US07461324B2 Parallel processing for decoding and cyclic redundancy checking for the reception of mobile radio signals 失效
标题翻译：用于解码和循环冗余校验的并行处理用于接收移动无线电信号
公开(公告)号：US07461324B2
公开(公告)日：2008-12-02
申请号：US11063949
申请日：2005-02-23
申请人： Jens Berkmann , Wolfgang Haas , Thomas Herndl , Gerald Hodits , Armin Häutle , Sasha Simeunovic
发明人： Jens Berkmann , Wolfgang Haas , Thomas Herndl , Gerald Hodits , Armin Häutle , Sasha Simeunovic
IPC分类号： H03M13/00
CPC分类号： H04L1/0059 , H03M13/09 , H04L1/0046 , H04L1/0054 , H04L1/0061
摘要： Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.
摘要翻译：根据由维特比追溯产生的解码的有效载荷信号位（am1，...，amA）和冗余校验位（pm1，...，pmL）的顺序，这些位中的一些位将通过分配装置（1）从前面到线性反馈移位寄存器（10），或者这些位中的一些位从后面通过分配装置（1）插入到线性反馈移位寄存器（10）或全部将它们从后面插入到线性反馈移位寄存器（20）中，分配的系数不变，或者它们全部从前面插入到移位寄存器中，分配的系数被反转。这允许在移位寄存器（10; 20）中的发送数据块上执行冗余校验处理，而不会临时存储由解码处理产生的位。

6. 发明申请

US20120178401A1 SYSTEM INCLUDING RECEIVER FRONT ENDS 有权
标题翻译：系统包括接收器前端
公开(公告)号：US20120178401A1
公开(公告)日：2012-07-12
申请号：US13424611
申请日：2012-03-20
申请人： Martin Flatscher , Manfred Greschitz , Thomas Herndl , Markus Dielacher
发明人： Martin Flatscher , Manfred Greschitz , Thomas Herndl , Markus Dielacher
IPC分类号： H04B1/16
CPC分类号： H04W52/0245 , Y02D70/00
摘要： An integrated circuit chip includes an output node, receiver front ends, and control logic. The receiver front ends are configured to receive an input signal. Each of the receiver front ends is configured to receive the input signal and provide an output signal at the output node. At least one of the receiver front ends is configured to selectively consume less power. The control logic is configured to select the number of receiver front ends providing an output signal to the output node based on a received signal strength indication.
摘要翻译：集成电路芯片包括输出节点，接收器前端和控制逻辑。接收器前端配置为接收输入信号。接收器前端中的每一个被配置为接收输入信号并在输出节点处提供输出信号。接收器前端中的至少一个被配置为选择性地消耗更少的功率。控制逻辑被配置为基于接收到的信号强度指示来选择向输出节点提供输出信号的接收机前端的数量。

7. 发明申请

US20080227235A1 Sensor Component And Method For Producing A Sensor Component 有权
标题翻译：传感器组件和传感器组件的制作方法
公开(公告)号：US20080227235A1
公开(公告)日：2008-09-18
申请号：US11692592
申请日：2007-03-28
申请人： Horst Theuss , Thomas Herndl , Werner Weber , Joachim Weitzel , Albert Auburger
发明人： Horst Theuss , Thomas Herndl , Werner Weber , Joachim Weitzel , Albert Auburger
IPC分类号： H01L21/00
CPC分类号： G01D11/245 , B60C23/0408 , G01L19/0061 , G01L19/086 , G01L19/148 , H01L2224/48091 , H01L2224/48472 , H01L2924/16195 , H01L2924/1627 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： A device for detecting a measured quantity has a sensor chip for detecting the measured quantity, a supply for providing a power supply, and an injection-molded enclosure for accommodating the sensor chip and the supply, the injection-molded enclosure including integrated conductive traces providing an electrical connection between the sensor chip and the supply.
摘要翻译：用于检测测量量的装置具有用于检测测量量的传感器芯片，用于提供电源的电源，以及用于容纳传感器芯片和电源的注塑外壳，注塑外壳包括提供传感器芯片和电源之间的电气连接。

8. 发明申请

US20050034046A1 Combined interleaver and deinterleaver, and turbo decoder comprising a combined interleaver and deinterleaver 审中-公开
标题翻译：组合交织器和去交织器，以及包括组合交织器和解交织器的turbo解码器
公开(公告)号：US20050034046A1
公开(公告)日：2005-02-10
申请号：US10920902
申请日：2004-08-18
申请人： Jens Berkmann , Thomas Herndl
发明人： Jens Berkmann , Thomas Herndl
IPC分类号： H03M13/27 , H03M13/29 , H03M13/00
CPC分类号： H03M13/2782 , H03M13/2714 , H03M13/2764 , H03M13/2771 , H03M13/2957
摘要： A combined interleaving and deinterleaving circuit (IDL1) has a first data memory (RAM) for temporary storage of the data to be interleaved and deinterleaved. A first address generator produces a sequence of sequential addresses, and a second address generator (AG) produces a sequence of addresses which represents the interleaving rule (α(i)). A logic means (XOR, MUX) causes the data memory (RAM) to be addressed by the second address generator (AG) in the interleaving mode for a read process and in the deinterleaving mode for a write process.
摘要翻译：组合交织和解交织电路（IDL1）具有第一数据存储器（RAM），用于临时存储待交织和解交织的数据。第一地址发生器产生顺序地址序列，第二地址生成器（AG）产生表示交织规则（α（i））的地址序列。逻辑装置（XOR，MUX）使得数据存储器（RAM）由第二地址发生器（AG）以用于读取处理的交错模式和用于写入处理的解交织模式来寻址。

9. 发明授权

US08638888B2 Analog correlation technique for ultra low power receivers 有权
标题翻译：超低功耗接收机的模拟相关技术
公开(公告)号：US08638888B2
公开(公告)日：2014-01-28
申请号：US13187855
申请日：2011-07-21
申请人： Christian Hambeck , Stefan Mahlknecht , Thomas Herndl , Franz Darrer , Jakob Jongsma
发明人： Christian Hambeck , Stefan Mahlknecht , Thomas Herndl , Franz Darrer , Jakob Jongsma
IPC分类号： H03D1/00
CPC分类号： H04B1/709
摘要： One embodiment of the present invention relates to an analog correlation unit comprising a plurality of parallel correlation components configured to operating according to an advanced switched-capacitor low pass filter principle that increases coding gain of the unit. Each correlation component comprises a sampling stage and a correlation stage. The sampling stage may comprise a switched capacitor configured to sample a received baseband signal to determine a value (e.g., polarity) of the baseband signal. The sampled baseband signal is provided to the correlation stages, which may respectively comprise a plurality of switched integrators configured to selectively receive and integrate the sampled baseband signal over time depending upon values (e.g., polarity) of the correlation code to generate voltage potential values. The analog correlation result is evaluated by a comparison of an adjustable threshold voltage with the difference between the output voltage potential values.
摘要翻译：本发明的一个实施例涉及一种模拟相关单元，包括多个并行相关分量，其被配置为根据提高单元的编码增益的高级开关电容器低通滤波器原理进行操作。每个相关分量包括采样阶段和相关阶段。采样级可以包括被配置为对接收的基带信号进行采样以确定基带信号的值（例如，极性）的开关电容器。将采样的基带信号提供给相关级，其可以分别包括多个开关积分器，其被配置为根据相关代码的值（例如，极性）随时间选择性地接收和积分采样的基带信号，以产生电压电位值。模拟相关结果通过可调阈值电压与输出电压电位差之间的差值进行比较来评估。

10. 发明申请

US20130022154A1 ANALOG CORRELATION TECHNIQUE FOR ULTRA LOW POWER RECEIVERS 有权
标题翻译：超低功率接收机的模拟相关技术
公开(公告)号：US20130022154A1
公开(公告)日：2013-01-24
申请号：US13187855
申请日：2011-07-21
申请人： Christian Hambeck , Stefan Mahlknecht , Thomas Herndl , Franz Darrer , Jakob Jongsma
发明人： Christian Hambeck , Stefan Mahlknecht , Thomas Herndl , Franz Darrer , Jakob Jongsma
IPC分类号： H04L27/00
CPC分类号： H04B1/709
摘要： One embodiment of the present invention relates to an analog correlation unit comprising a plurality of parallel correlation components configured to operating according to an advanced switched-capacitor low pass filter principle that increases coding gain of the unit. Each correlation component comprises a sampling stage and a correlation stage. The sampling stage may comprise a switched capacitor configured to sample a received baseband signal to determine a value (e.g., polarity) of the baseband signal. The sampled baseband signal is provided to the correlation stages, which may respectively comprise a plurality of switched integrators configured to selectively receive and integrate the sampled baseband signal over time depending upon values (e.g., polarity) of the correlation code to generate voltage potential values. The analog correlation result is evaluated by a comparison of an adjustable threshold voltage with the difference between the output voltage potential values.
摘要翻译：本发明的一个实施例涉及一种模拟相关单元，包括多个并行相关分量，其被配置为根据提高单元的编码增益的高级开关电容器低通滤波器原理进行操作。每个相关分量包括采样阶段和相关阶段。采样级可以包括被配置为对接收的基带信号进行采样以确定基带信号的值（例如，极性）的开关电容器。将采样的基带信号提供给相关级，其可以分别包括多个开关积分器，其被配置为根据相关代码的值（例如，极性）随时间选择性地接收和积分采样的基带信号，以产生电压电位值。模拟相关结果通过可调阈值电压与输出电压电位差之间的差值进行比较来评估。

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