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    • 3. 发明申请
    • CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE
    • 电路结构和方法与配置阻塞电磁边缘干扰的波纹层
    • US20100032814A1
    • 2010-02-11
    • US12188243
    • 2008-08-08
    • Choongyeun CHODaeik KIMJonghae KIMMoon Ju KIMJames Randal MOULIC
    • Choongyeun CHODaeik KIMJonghae KIMMoon Ju KIMJames Randal MOULIC
    • H01L23/552H01L21/4763
    • H01L23/5225H01L23/552H01L2924/0002H01L2924/00
    • Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.
    • 提供了后端行(BEOL)电路结构和方法来阻止外部来源或内部产生的电磁边缘干扰。 一个这样的BEOL电路结构包括支撑一个或多个集成电路的半导体衬底和设置在半导体衬底上的多个BEOL层。 多个BEOL层延伸到电路结构的边缘并且包括邻近电路结构的边缘布置的至少一个垂直延伸的导电图案。 至少部分地由设置在多个BEOL层中的多个元件限定垂直延伸的导电图案。 多个元件在电路结构的边缘沿其第一方向或第二方向均匀地排列在其至少一部分上。 多个元件的大小和尺寸设置在第一方向或第二方向上,以阻止特定波长的电磁干扰通过。
    • 4. 发明申请
    • CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE
    • 电路结构和方法与配置阻塞电磁边缘干扰的波纹层
    • US20120135599A1
    • 2012-05-31
    • US13369592
    • 2012-02-09
    • Choongyeun CHODaeik KIMJonghae KIMMoon Ju KIMJames Randal MOULIC
    • Choongyeun CHODaeik KIMJonghae KIMMoon Ju KIMJames Randal MOULIC
    • H01L21/768
    • H01L23/5225H01L23/552H01L2924/0002H01L2924/00
    • Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.
    • 提供了后端行(BEOL)电路结构和方法来阻止外部来源或内部产生的电磁边缘干扰。 一个这样的BEOL电路结构包括支撑一个或多个集成电路的半导体衬底和设置在半导体衬底上的多个BEOL层。 多个BEOL层延伸到电路结构的边缘并且包括邻近电路结构的边缘布置的至少一个垂直延伸的导电图案。 至少部分地由设置在多个BEOL层中的多个元件限定垂直延伸的导电图案。 多个元件在电路结构的边缘沿其第一方向或第二方向均匀地排列在其至少一部分上。 多个元件的大小和尺寸设置在第一方向或第二方向上,以阻止特定波长的电磁干扰通过。
    • 6. 发明申请
    • TRANSITIONING DIGITAL INTEGRATED CIRCUIT FROM STANDBY MODE TO ACTIVE MODE VIA BACKGATE CHARGE TRANSFER
    • 通过背板充电转移将数字集成电路从待机模式转换到主动模式
    • US20100060344A1
    • 2010-03-11
    • US12206124
    • 2008-09-08
    • Choongyeun CHODaeik KIMJonghae KIMMoon Ju KIM
    • Choongyeun CHODaeik KIMJonghae KIMMoon Ju KIM
    • G05F1/10H01S4/00
    • H03K19/0016Y10T29/49002
    • Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.
    • 提供了电路和方法,以便于将数字电路从背栅极偏置待机模式转换到主动模式。 数字电路包括半导体衬底,至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管,至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管 基板和背栅控制电路。 背栅控制电路电耦合到p型阱和n型阱,以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源 模式,通过自动将电荷从n型阱转移到p型阱,直到达到阱电压阈值,表明晶体管从背栅极偏置待机模式到活动模式的完成转变。
    • 7. 发明申请
    • CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYER(S) CONFIGURED TO BLOCK ELECTROMAGNETIC INTERFERENCE
    • 具有配置为阻塞电磁干扰的波形层的电路结构和方法
    • US20080277773A1
    • 2008-11-13
    • US11747342
    • 2007-05-11
    • Dae Ik KIMJonghae KIMMoon Ju KIMChoongyeun (Chuck) CHO
    • Dae Ik KIMJonghae KIMMoon Ju KIMChoongyeun (Chuck) CHO
    • H01L23/48H01L21/00
    • H01L23/552H01L2924/0002H01L2924/00
    • Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.
    • 提供后端(BEOL)电路结构和方法来阻止外部来源或内部产生的电磁干扰。 一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。 至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。 多个元件的大小和位置在第一和第二方向中的至少一个方向上,以阻止特定波长的电磁干扰通过。 在一个实施方案中,第一BEOL层的第一导电图案使电磁干扰偏振,并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。
    • 8. 发明申请
    • SYSTEM AND METHOD FOR MONITORING RELIABILITY OF A DIGITAL SYSTEM
    • 用于监测数字系统可靠性的系统和方法
    • US20080270049A1
    • 2008-10-30
    • US11742018
    • 2007-04-30
    • Dae Ik KIMJonghae KIMMoon Ju KIMJames R. MOULICHong Hua SONG
    • Dae Ik KIMJonghae KIMMoon Ju KIMJames R. MOULICHong Hua SONG
    • G01R31/00
    • G01R31/31937G01R31/31725
    • System and method are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades past a specified threshold. The technique includes implementing a ring oscillator sensor in association with the digital system, wherein logic and/or device percent composition of the ring oscillator sensor mirrors percent composition thereof within the digital system. Counter logic is coupled to the ring oscillator sensor for converting outputted count signals to an oscillation frequency, and control logic is coupled to the counter logic for periodically evaluating oscillation frequency of the ring oscillator sensor and generating a warning signal indicative of reliability degradation if at least one of: (i) a measured or estimated oscillation frequency is below a warning threshold frequency; or (ii) a measured or estimated rate of change in a difference between measured oscillation frequencies exceeds an acceptable rate of change threshold.
    • 提供系统和方法用于连续监视数字系统的可靠性或老化,并且如果数字系统操作降低到指定的阈值以上,则发出警告信号。 该技术包括实现与数字系统相关联的环形振荡器传感器,其中环形振荡器传感器的逻辑和/或设备百分比组成反映数字系统内的其组成的百分比。 计数器逻辑耦合到环形振荡器传感器,用于将输出的计数信号转换为振荡频率,并且控制逻辑耦合到计数器逻辑,用于周期性评估环形振荡器传感器的振荡频率,并产生指示可靠性降级的警告信号,如果至少 以下之一:(i)测量或估计的振荡频率低于警告阈值频率; 或者(ii)所测量的振荡频率之间的测量或估计的变化率超过可接受的变化率阈值。
    • 9. 发明申请
    • MONITORING RELIABILITY OF A DIGITAL SYSTEM
    • 监测数字系统的可靠性
    • US20080253437A1
    • 2008-10-16
    • US11733318
    • 2007-04-10
    • Dae Ik KIMJonghae KIMMoon Ju KIMJames R. MOULICHong Hua SONG
    • Dae Ik KIMJonghae KIMMoon Ju KIMJames R. MOULICHong Hua SONG
    • H04B17/00
    • G06F11/008
    • Method, system and article of manufacture are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades to or past a specified threshold. The technique includes periodically determining a maximum frequency of operation of the digital system, and generating a warning signal indicative of a reliability degradation of the digital system if at least one of: (i) a measured or estimated maximum frequency of operation of the digital system is below a warning threshold frequency of operation of the digital system, wherein the warning threshold frequency is greater than or equal to a manufacturer specified minimum frequency of operation for the digital system; or (ii) a rate of change in the difference between measured maximum frequencies of operation of the digital system exceeds an acceptable rate of change threshold for the digital system.
    • 提供了方法,系统和制造品,用于连续监视数字系统的可靠性或老化,并且如果数字系统操作降低到或超过指定阈值,则发出警告信号。 该技术包括周期性地确定数字系统的最大操作频率,以及产生指示数字系统的可靠性劣化的警告信号,如果以下至少一个:(i)数字系统的测量或估计的最大操作频率 低于数字系统的警告阈值操作频率,其中警告阈值频率大于或等于制造商规定的数字系统的最小操作频率; 或者(ii)数字系统的测量的最大操作频率之间的差异的变化率超过数字系统的可接受的变化率阈值。