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1. 发明授权

US5481126A Semiconductor-on-insulator electronic devices having trench isolated monocrystalline active regions 失效
标题翻译：具有沟槽隔离单晶有源区的绝缘体上半导体电子器件
公开(公告)号：US5481126A
公开(公告)日：1996-01-02
申请号：US313893
申请日：1994-09-27
申请人： Chitra K. Subramanian , Gerold W. Neudeck
发明人： Chitra K. Subramanian , Gerold W. Neudeck
IPC分类号： H01L27/06 , H01L29/06 , H01L29/786 , H01L29/80 , H01L31/112
CPC分类号： H01L29/0653 , H01L27/0623 , H01L29/0649 , H01L29/78654
摘要： A semiconductor-on-insulator (SOI) electronic device includes a monocrystalline semiconductor substrate and at least one trench therein. A trench insulating layer is provided on a bottom the trench for electrical isolation and a monocrystalline semiconducting region is also included in the trench, on the trench insulating layer. The semiconducting region preferably includes epitaxially overgrown silicon (EOS) which is grown from an exposed sidewall of the trench. An active region of the electronic device is also included in the semiconductor layer. Second, third, and additional active regions of the electronic device, if any, may also be included in the semiconducting region or in additional semiconducting regions which are provided in additional trenches. The semiconductor substrate may also include one or more active regions of the electronic device.
摘要翻译：绝缘体上半导体（SOI）电子器件包括单晶半导体衬底及其中的至少一个沟槽。沟槽绝缘层设置在用于电隔离的沟槽的底部，并且在沟槽绝缘层中的沟槽中还包括单晶半导体区域。半导体区域优选地包括从沟槽的暴露的侧壁生长的外延长满的硅（EOS）。电子器件的有源区也包括在半导体层中。电子器件的第二，第三和另外的有源区（如果有的话）也可以被包括在半导体区域中或在另外的沟槽中提供的附加的半导体区域中。半导体衬底还可以包括电子器件的一个或多个有源区。

2. 发明授权

US5494837A Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls 失效
标题翻译：通过从沟槽侧壁生长单晶半导体区域来形成绝缘体上半导体电子器件的方法
公开(公告)号：US5494837A
公开(公告)日：1996-02-27
申请号：US312874
申请日：1994-09-27
申请人： Chitra K. Subramanian , Gerold W. Neudeck
发明人： Chitra K. Subramanian , Gerold W. Neudeck
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/12 , H01L29/06 , H01L29/78 , H01L21/8232
CPC分类号： H01L27/1203 , H01L21/8249 , H01L27/0623 , H01L29/0653 , H01L29/7834
摘要： A method of forming a semiconductor-on-insulator (SOI) electronic device includes the steps of etching a semiconductor substrate to form a plurality of adjacent trenches therein and then forming electrically insulating layers on bottoms of the trenches. Epitaxial lateral overgrowth (ELO) is then performed to grow respective monocrystalline semiconducting regions in the trenches. These semiconducting regions are preferably grown from a sidewall of each trench onto a respective insulating layer and fill each trench. Monocrystalline active regions of the electronic device are then formed in the semiconducting regions and also in the substrate, adjacent the trench sidewalls. For example, a monocrystalline trench isolated extrinsic base region of a bipolar junction transistor (BJT) can be formed in a semiconducting region in a respective trench, and a corresponding intrinsic base region and an intrinsic collector region can be formed in the substrate, adjacent the semiconducting region. Alternatively, trench isolated source and drain regions of a field effect transistor (FET) can be formed in one or more adjacent semiconducting regions and the corresponding channel region of the FET can be formed therebetween.
摘要翻译：一种形成绝缘体上半导体（SOI）电子器件的方法包括以下步骤：蚀刻半导体衬底以在其中形成多个相邻的沟槽，然后在沟槽底部形成电绝缘层。然后进行外延横向过度生长（ELO）以在沟槽中生长相应的单晶半导体区域。这些半导体区域优选地从每个沟槽的侧壁生长到相应的绝缘层上并填充每个沟槽。然后，电子器件的单晶有源区形成在半导体区域中，并且在衬底中形成，与沟槽侧壁相邻。例如，可以在各沟槽中的半导体区域中形成双极结型晶体管（BJT）的单晶沟隔离外部基极区域，并且可以在衬底中形成相应的本征基极区域和固有集电极区域半导体区域。或者，可以在一个或多个相邻半导体区域中形成场效应晶体管（FET）的沟槽隔离源极和漏极区域，并且可以在其间形成FET的对应沟道区域。

3. 发明授权

US07154772B2 MRAM architecture with electrically isolated read and write circuitry 有权
标题翻译：具有电隔离读写电路的MRAM架构
公开(公告)号：US07154772B2
公开(公告)日：2006-12-26
申请号：US11076523
申请日：2005-03-09
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。类似地，写入电压不必降低以适应低电压型晶体管。整体存储器的大小保持有效小，同时提高性能。存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

4. 发明授权

US06760266B2 Sense amplifier and method for performing a read operation in a MRAM 有权
公开(公告)号：US06760266B2
公开(公告)日：2004-07-06
申请号：US10185566
申请日：2002-06-28
申请人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/16 , G11C7/062 , G11C27/02
摘要： A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

5. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

6. 发明授权

US07532533B2 Antifuse circuit and method for selectively programming thereof 有权
标题翻译：防腐电路及其选择性编程方法
公开(公告)号：US07532533B2
公开(公告)日：2009-05-12
申请号：US11737506
申请日：2007-04-19
申请人： Thomas W. Andre , Chitra K. Subramanian
发明人： Thomas W. Andre , Chitra K. Subramanian
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C11/1673 , G11C11/1695 , G11C11/5692 , G11C17/02
摘要： An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.
摘要翻译：反熔丝电路以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝是否已经被预先编程为响应于编程电压的低电阻状态。读出放大器提供电阻状态信号。多个参考磁隧道结并联耦合到读出放大器，每个具有一个范围内的电阻，以提供可由感测放大器确定的不同于MTJ反熔丝的每个电阻状态的集合电阻。写入电路选择性地提供足以在写入电路被编程反熔丝磁性隧道结时产生编程电压的电流。当检测到MTJ反熔丝中的电阻变化时，写入电路减少提供给反熔丝的电流。多个反熔丝可以同时编程。调整晶体管的栅极氧化物厚度以获得最佳性能。

7. 发明授权

US06944052B2 Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics 失效
公开(公告)号：US06944052B2
公开(公告)日：2005-09-13
申请号：US10304625
申请日：2002-11-26
申请人： Chitra K. Subramanian , Joseph J. Nahas
发明人： Chitra K. Subramanian , Joseph J. Nahas
IPC分类号： G11C11/15 , G11C11/16 , H01L27/22 , H01L27/24 , G11C11/14
CPC分类号： H01L27/224 , G11C11/16
摘要： In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) (54) cell is stacked with an asymmetric tunnel device (56). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers (42, 46) separated by an insulator (44). The asymmetric tunnel device (56) is electrically connected in series with the MTJ cell and is formed by at least two conductive layers (48, 52) separated by an insulator (50). The asymmetric tunnel device may be a MIM (56), MIMIM (80) or a MIIM (70). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.

8. 发明授权

US06711052B2 Memory having a precharge circuit and method therefor 有权
标题翻译：具有预充电电路的存储器及其方法
公开(公告)号：US06711052B2
公开(公告)日：2004-03-23
申请号：US10185488
申请日：2002-06-28
申请人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C700
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。每个具有多个串联级的可切换电流镜接收公共参考电流。定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。位线在公共端连接在一起，字线在公共端连接在一起。通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。位线组可以通过金属选项来连接，以调整编程电流的转换时间。

9. 发明授权

US06657889B1 Memory having write current ramp rate control 有权
标题翻译：具有写入电流斜坡率控制的存储器
公开(公告)号：US06657889B1
公开(公告)日：2003-12-02
申请号：US10185075
申请日：2002-06-28
申请人： Chitra K. Subramanian , Thomas W. Andre , Bradley J. Garni , Halbert S. Lin , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Bradley J. Garni , Halbert S. Lin , Joseph J. Nahas
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。每个具有多个串联级的可切换电流镜接收公共参考电流。定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。位线在公共端连接在一起，字线在公共端连接在一起。通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。位线组可以通过金属选项来连接，以调整编程电流的转换时间。

10. 发明授权

US5665202A Multi-step planarization process using polishing at two different pad pressures 失效
标题翻译：使用两种不同压力下的抛光进行多步平面化处理
公开(公告)号：US5665202A
公开(公告)日：1997-09-09
申请号：US562440
申请日：1995-11-24
申请人： Chitra K. Subramanian , Asanga H. Perera , James D. Hayden , Subramoney V. Iyer
发明人： Chitra K. Subramanian , Asanga H. Perera , James D. Hayden , Subramoney V. Iyer
IPC分类号： H01L21/3105 , H01L21/306
CPC分类号： H01L21/31053
摘要： A process for polish planarizing a fill material (40) overlying a semiconductor substrate (30) includes a multi-step polishing process. In one embodiment, a second planarization layer (42) is deposited over a fill material (40) and a portion of the fill material (40) is removed leaving a remaining portion (44). The pad pressure of a CMP apparatus (20) is adjusted such that a first pressure is generated during the polishing process. Then, the remaining portion (44) is removed, while operating the CMP apparatus (20) at a second pad pressure. The selectivity of the polishing process is maintained by reducing the pad pressure during the second polishing step. In a second embodiment, after the first polishing step is performed, the remaining portion (44) is removed by an etching process using a portion (46) of second planarization layer (42).
摘要翻译：抛光平面化覆盖半导体衬底（30）的填充材料（40）的工艺包括多步抛光工艺。在一个实施例中，第二平坦化层（42）沉积在填充材料（40）上，并且去除填充材料（40）的一部分，留下剩余部分（44）。调整CMP装置（20）的衬垫压力，使得在抛光过程中产生第一压力。然后，在第二焊盘压力下操作CMP装置（20）的同时去除剩余部分（44）。通过在第二抛光步骤期间减小垫压力来维持抛光工艺的选择性。在第二实施例中，在执行第一抛光步骤之后，通过使用第二平坦化层（42）的部分（46）的蚀刻工艺去除剩余部分（44）。

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