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1. 发明授权

US07154772B2 MRAM architecture with electrically isolated read and write circuitry 有权
标题翻译：具有电隔离读写电路的MRAM架构
公开(公告)号：US07154772B2
公开(公告)日：2006-12-26
申请号：US11076523
申请日：2005-03-09
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。类似地，写入电压不必降低以适应低电压型晶体管。整体存储器的大小保持有效小，同时提高性能。存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

2. 发明授权

US06760266B2 Sense amplifier and method for performing a read operation in a MRAM 有权
公开(公告)号：US06760266B2
公开(公告)日：2004-07-06
申请号：US10185566
申请日：2002-06-28
申请人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/16 , G11C7/062 , G11C27/02
摘要： A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

3. 发明授权

US06738303B1 Technique for sensing the state of a magneto-resistive random access memory 有权
标题翻译：用于感测磁阻随机存取存储器的状态的技术
公开(公告)号：US06738303B1
公开(公告)日：2004-05-18
申请号：US10305736
申请日：2002-11-27
申请人： Chitra K. Subramanian , Bradley J. Garni
发明人： Chitra K. Subramanian , Bradley J. Garni
IPC分类号： G11C702
CPC分类号： G11C11/15
摘要： The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.
摘要翻译：当MRAM单元的磁隧道结（MTJ）具有从用于偏置的最大电压的偏差减小时，检测到MRAM单元的状态。在一个示例中，所选择的单元的MTJ和参考单元的MTJ均被偏置到第一电压。然后，MTJs渐近地将该偏置（基于利用位线电容和MTJ电阻的RC时间常数）放电到较低电压（例如接地），但是由于MTJ电阻差，对于所选择的单元与参考单元不同的速率。在预定时间，检测到电压差。在另一个例子中，MTJs被预充电到低电压，然后渐近地向更高的电压驱动。因此，在感测两种情况下，MTJ两端的电压小于所使用的偏置电压。

4. 发明授权

US06621729B1 Sense amplifier incorporating a symmetric midpoint reference 有权
标题翻译：包含对称中点参考的感应放大器
公开(公告)号：US06621729B1
公开(公告)日：2003-09-16
申请号：US10185224
申请日：2002-06-28
申请人： Bradley J. Garni , Chitra K. Subramanian , Joseph J. Nahas , Thomas W. Andre
发明人： Bradley J. Garni , Chitra K. Subramanian , Joseph J. Nahas , Thomas W. Andre
IPC分类号： G11C1100
CPC分类号： G11C11/14 , G11C7/062 , G11C7/067 , G11C2207/063
摘要： A sense amplifier (10) develops internally a midpoint reference current from two reference bits. The midpoint reference current is used to sense the state of a memory bit having at least two distinct resistance states (H and L) by determining whether the sense memory bit develops a larger or smaller current. The midpoint reference current is developed within a single sense amplifier. Predetermined bias voltages are developed from each of a data bit cell, a reference cell programmed to a high state and a reference cell programmed to a low state. Currents are developed from the bias voltages and summed to create the midpoint reference current. A current differential amplifier senses whether the bit input has a high or low resistive state and outputs a voltage indicative of the sensed memory state.
摘要翻译：读出放大器（10）内部产生来自两个参考位的中点参考电流。中点参考电流用于通过确定感测存储器位是否产生较大或更小的电流来感测具有至少两个不同电阻状态（H和L）的存储器位的状态。在单个读出放大器内开发中点参考电流。从数据位单元，被编程为高状态的参考单元和被编程为低状态的参考单元中的每一个产生预定的偏置电压。电流从偏置电压开始，并相加以产生中点参考电流。电流差分放大器感测位输入是否具有高电阻状态或低电阻状态，并且输出指示感测到的存储器状态的电压。

5. 发明授权

US06600690B1 Sense amplifier for a memory having at least two distinct resistance states 失效
标题翻译：用于具有至少两个不同电阻状态的存储器的感测放大器
公开(公告)号：US06600690B1
公开(公告)日：2003-07-29
申请号：US10184784
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni , Chitra K. Subramanian
发明人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/14 , G11C7/067 , G11C7/14 , G11C2207/063
摘要： In a memory, a sensing system detects bit states using one data and two reference inputs, to sense a difference in conductance of a selected memory bit cell and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell in the high conductance state and a memory cell in the low conductance state. The data input is coupled to the selected memory bit cell. The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages amplifies the sense amplifier output without injecting parasitic errors.
摘要翻译：在存储器中，感测系统使用一个数据和两个参考输入来检测位状态，以感测所选存储位单元的电导差和中点参考电导。产生参考电导作为高电导状态的存储单元的平均电导和低电导状态的存储单元。数据输入耦合到所选择的存储器位单元。两个参考输入分别以高和低电导存储器状态耦合到存储器单元。读出放大器使用电流偏置或电压偏置来在位单元之间的预定电压范围内施加感测电压。耦合到读出放大器的互补输出的电容由电路设计来平衡。在一种形式中，两个参考输入是内部连接的。几个增益级之一放大读出放大器输出，而不会注入寄生错误。

6. 发明授权

US06580298B1 Three input sense amplifier and method of operation 有权
标题翻译：三路输入读出放大器及其操作方法
公开(公告)号：US06580298B1
公开(公告)日：2003-06-17
申请号：US10186363
申请日：2002-06-28
申请人： Chitra K. Subramanian , Bradley J. Garni , Joseph J. Nahas , Thomas W. Andre
发明人： Chitra K. Subramanian , Bradley J. Garni , Joseph J. Nahas , Thomas W. Andre
IPC分类号： G11C706
CPC分类号： G11C7/062 , G11C11/16 , G11C2207/063
摘要： A sense amplifier having three inputs determines the state of a memory bit cell by converting a bit input voltage, a high reference voltage, and a low reference voltage to respective current values. Current differences are formed between a bit current and a high reference current, and between a low reference current and a bit current. Current mirrors (154, 158 and 170, 166) and loads (160 and 168) are used in conjunction with current steering circuitry (150, 140, 142 and 162) to form the difference of the bit current and the high reference current and also form the difference of the low reference current and the bit current. Additionally, the sense amplifier drives differential outputs (OUT and OUT13B) to reflect the difference between the two current differential quantities.
摘要翻译：具有三个输入的读出放大器通过将位输入电压，高参考电压和低参考电压转换为相应的电流值来确定存储器位单元的状态。在位电流和高参考电流之间以及低参考电流和位电流之间形成电流差。电流镜（154,158和170,166）和负载（160和168）与电流控制电路（150,140,142和162）结合使用以形成比特电流和高参考电流的差异形成低参考电流和位电流的差异。此外，读出放大器驱动差分输出（OUT和OUT13B）以反映两个电流差分量之间的差异。

7. 发明授权

US06657889B1 Memory having write current ramp rate control 有权
标题翻译：具有写入电流斜坡率控制的存储器
公开(公告)号：US06657889B1
公开(公告)日：2003-12-02
申请号：US10185075
申请日：2002-06-28
申请人： Chitra K. Subramanian , Thomas W. Andre , Bradley J. Garni , Halbert S. Lin , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Bradley J. Garni , Halbert S. Lin , Joseph J. Nahas
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。每个具有多个串联级的可切换电流镜接收公共参考电流。定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。位线在公共端连接在一起，字线在公共端连接在一起。通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。位线组可以通过金属选项来连接，以调整编程电流的转换时间。

8. 发明授权

US06903964B2 MRAM architecture with electrically isolated read and write circuitry 失效
标题翻译：具有电隔离读写电路的MRAM架构
公开(公告)号：US06903964B2
公开(公告)日：2005-06-07
申请号：US10185868
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
IPC分类号： G11C11/16 , G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。类似地，写入电压不必降低以适应低电压型晶体管。整体存储器的大小保持有效小，同时提高性能。存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

9. 发明授权

US06538940B1 Method and circuitry for identifying weak bits in an MRAM 失效
标题翻译：用于识别MRAM中弱位的方法和电路
公开(公告)号：US06538940B1
公开(公告)日：2003-03-25
申请号：US10255303
申请日：2002-09-26
申请人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni
发明人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni
IPC分类号： G11C700
CPC分类号： G11C29/12005 , G11C11/16 , G11C29/12
摘要： A memory (10, 60) having at least two resistance states is tested. In one form, the memory includes a first transistor (16, 68) having a current electrode coupled to a memory cell (14, 64) and a second transistor (26, 66) having a current electrode coupled to a reference memory cell (28, 74). The control electrode of the first transistor receives either a first reference voltage or a second reference voltage based on a test control signal, and the control electrode of a second transistor receives the first reference voltage. In a test mode, after the memory cell is programmed with a resistance state, the second reference voltage (different from the first reference voltage) is provided to the first transistor. The memory cell is then read to determine whether the memory can sense the previously programmed resistance state. In one embodiment, this test mode can be used to identify weak bits in the memory.
摘要翻译：测试具有至少两个电阻状态的存储器（10,60）。在一种形式中，存储器包括具有耦合到存储器单元（14,64）的电流电极的第一晶体管（16,68）和具有耦合到参考存储器单元（28）的电流电极的第二晶体管（26,66），74）。第一晶体管的控制电极基于测试控制信号接收第一参考电压或第二参考电压，并且第二晶体管的控制电极接收第一参考电压。在测试模式中，在存储单元被编程为电阻状态之后，将第二参考电压（不同于第一参考电压）提供给第一晶体管。然后读取存储器单元以确定存储器是否可以感测到先前编程的电阻状态。在一个实施例中，该测试模式可用于识别存储器中的弱位。

10. 发明授权

US08319548B2 Integrated circuit having low power mode voltage regulator 有权
标题翻译：集成电路具有低功耗模式电压调节器
公开(公告)号：US08319548B2
公开(公告)日：2012-11-27
申请号：US12622277
申请日：2009-11-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.
摘要翻译：电压调节器调节节点处的电压，并且具有耦合到节点的电路以向节点提供电流。耦合在节点和第一电源电压端子之间的调节晶体管具有并联耦合的禁用晶体管，并且通过将第一电源电压端子直接连接到节点来选择性地禁止。反相级具有连接到调节晶体管的输出端。负载晶体管具有耦合到第二电源电压端子的第一电流电极和连接在一起并耦合到反相级的输入端的控制电极和第二电流电极。感测晶体管具有耦合到负载晶体管的第二电流电极的第一电流电极，直接连接到节点的控制电极和耦合到第一电源电压端子的第二电流电极。

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