专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100100860A1 METHOD AND APPARATUS FOR DEBUGGING AN ELECTRONIC SYSTEM DESIGN (ESD) PROTOTYPE 审中-公开
标题翻译：用于调试电子系统设计（ESD）原型的方法和装置
公开(公告)号：US20100100860A1
公开(公告)日：2010-04-22
申请号：US12255606
申请日：2008-10-21
申请人： Chioumin M. Chang , Thomas B. Huang , Huan-Chih Tsai
发明人： Chioumin M. Chang , Thomas B. Huang , Huan-Chih Tsai
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Using a vector-based emulation technique, a hardware-based prototyping system reduces time-consuming recompilation and reduces the iteration time for a verification run. The vector-based emulation technique takes advantage of information derived from user-defined probe points, automatically generated probe points and low-latency snapshots. Using a bounded-cycle simulation technique, the hardware-based prototyping system can provide complete or partial simulation traces covering interested signals and can efficiently evaluates assertions. A user is therefore able to debug in a real system test and to identify causes of fault conditions interactively under a controlled vector debugging environment.
摘要翻译：使用基于向量的仿真技术，基于硬件的原型系统可以减少耗时的重新编译，并减少验证运行的迭代时间。基于矢量的仿真技术利用从用户定义的探测点，自动生成的探测点和低延迟快照得到的信息。使用有界循环模拟技术，基于硬件的原型系统可以提供涵盖感兴趣信号的完整或部分模拟轨迹，并可以有效地评估断言。因此，用户能够在真实的系统测试中进行调试，并在受控的向量调试环境下交互地识别故障条件的原因。

2. 发明申请

US20120005547A1 SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING 审中-公开
标题翻译：用于原型调试的可扩展系统调试器
公开(公告)号：US20120005547A1
公开(公告)日：2012-01-05
申请号：US12827917
申请日：2010-06-30
申请人： Chioumin M. Chang , Thomas B. Huang , Huan-Chih Tsai , Ting-Mao Chang
发明人： Chioumin M. Chang , Thomas B. Huang , Huan-Chih Tsai , Ting-Mao Chang
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/261
摘要： A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more programmable embedded debug circuits each receiving a first group of selected signals from the logic circuit under verification and providing control signals for (1) selecting a portion of the first group of selected signals, or (2) affecting the values of a second group of selected signals in the logic circuit under verification based on a portion of the first group of selected signals satisfying a predetermined triggering condition, wherein the programmable embedded debug circuits each including a built-in memory for storing signal vectors, the programmable embedded debug circuits each being configured according to a trigger specification defining one or more trigger states and triggering conditions; and (iii) a local debugging controller that controls programmable embedded debug circuits and transfers signal vectors between the built-in memories of the programmable embedded debug circuits and the vector processor interface bus; and (c) a vector processor which controls transferring of signal vectors between the host processor and the vector processor interface bus.
摘要翻译：由主处理器通过主机总线控制的原型调试系统包括：（a）向量处理器接口总线; （b）一个或多个可编程逻辑电路，其中至少一个被提供用于实现：（i）正在验证的逻辑电路; （ii）一个或多个可编程嵌入式调试电路，每个接收来自所述逻辑电路的第一组选定信号，并且提供用于（1）选择所述第一组选定信号的一部分的控制信号，或（2）影响所述值基于满足预定触发条件的所述第一组选择信号的一部分，所述逻辑电路中的所选逻辑电路中的第二组选择信号，其中所述可编程嵌入式调试电路各自包括用于存储信号向量的内置存储器，所述可编程嵌入式调试电路各自根据定义一个或多个触发状态和触发条件的触发规范进行配置; 和（iii）本地调试控制器，其控制可编程嵌入式调试电路并在可编程嵌入式调试电路的内置存储器和矢量处理器接口总线之间传送信号矢量; 以及（c）矢量处理器，其控制主处理器和矢量处理器接口总线之间的信号矢量的传送。

3. 发明申请

US20110289469A1 VIRTUAL INTERCONNECTION METHOD AND APPARATUS 审中-公开
标题翻译：虚拟互连方法和设备
公开(公告)号：US20110289469A1
公开(公告)日：2011-11-24
申请号：US12785283
申请日：2010-05-21
申请人： Thomas B. Huang , Chioumin M. Chang , Huan-Chih Tsai , Ting-Mao Chang
发明人： Thomas B. Huang , Chioumin M. Chang , Huan-Chih Tsai , Ting-Mao Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuits each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions. The prototyping system is associated with a method for prototyping an electronic design, which includes (i) compiling an electronic design into (a) multiple partitions, each partition being compiled for implementation in a programmable logic circuit (e.g., a field programmable gate array integrated circuit), and (b) multiple connections that connect signals between the partition; and (ii) compiling into each programmable logic circuit an interface circuit module for managing the connections using a virtual interconnection technique.
摘要翻译：原型系统包括（i）具有用于与主处理器通信的接口的矢量处理器和用于调度矢量的第二接口（例如，矢量处理器总线）; （ii）多个可编程逻辑电路，每个可编程逻辑电路都耦合到第二接口以接收发送的矢量; （iii）编译器，用于（a）将电子电路划分成多个分区，将每个分区分配给可编程逻辑电路之一，（b）提供多个连接，每个连接提供用于在分区之间连接信号，（c）可编程逻辑电路，使用虚拟互连技术管理分区之间的连接的接口电路模块，以及（d）分配物理互连资源，例如可编程逻辑电路的引脚和物理线。首先进一步分配分区之间的至少一个虚拟互连（辅助I / O），以实现分区之间的连接。原型系统与用于原型设计电子设计的方法相关联，其包括（i）将电子设计编译成（a）多个分区，每个分区被编译用于在可编程逻辑电路中实现（例如，集成的现场可编程门阵列电路），和（b）连接分区之间的信号的多个连接; 和（ii）将每个可编程逻辑电路编译成用于使用虚拟互连技术来管理连接的接口电路模块。

4. 发明申请

US20100305933A1 Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution 审中-公开
标题翻译：使用矢量替换的矢量仿真验证逻辑电路的方法和装置
公开(公告)号：US20100305933A1
公开(公告)日：2010-12-02
申请号：US12476012
申请日：2009-06-01
申请人： Chioumin M. Chang , Thomas B. Huang , Huan-Chih Tsai , Ting-Mao Chang
发明人： Chioumin M. Chang , Thomas B. Huang , Huan-Chih Tsai , Ting-Mao Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing emulation vectors for use in a vector emulation of the logic circuit in the prototyping system; (c) setting one or more vector substitution points; (d) preparing one or more packet vectors at each vector substitution point for replacing emulation vectors in the vector emulation; (e) performing the vector emulation using the emulation vectors until one of the vector substitution points is reached; and (f) substituting packet vectors for the corresponding emulation vectors at vector substitution point and continuing the vector emulation.
摘要翻译：用于验证原型系统中的逻辑电路的方法包括（a）配置原型系统的可编程逻辑电路以实现逻辑电路并实现用于访问逻辑电路的内部节点的探针电路; （b）准备用于原型系统逻辑电路的矢量仿真中的仿真矢量; （c）设置一个或多个向量替换点; （d）在每个向量替换点处准备一个或多个分组向量以替换所述向量仿真中的仿真向量; （e）使用仿真矢量执行矢量仿真，直到达到矢量替代点之一; 和（f）在矢量替换点处将分组向量替换为对应的仿真矢量并继续矢量仿真。

5. 发明申请

US20090150839A1 INTEGRATED PROTOTYPING SYSTEM FOR VALIDATING AN ELECTRONIC SYSTEM DESIGN 失效
标题翻译：用于验证电子系统设计的集成原型系统
公开(公告)号：US20090150839A1
公开(公告)日：2009-06-11
申请号：US12110233
申请日：2008-04-25
申请人： Thomas B. Huang , Chioumin M. Chang
发明人： Thomas B. Huang , Chioumin M. Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator.
摘要翻译：提出了一种综合原型系统（IPS），用于验证和验证具有分层设计元素（HDE）的电子系统设计（ESD）。 IPS具有：a）具有仿真定时基的可编程逻辑器件（RPLD）和用于编程和模拟在确定交换向量时的HDE的RPLD接口。 RPLD还可切换地耦合到许多外部外围电子设备（PED），b）EDA模拟器，用于在交换向量的同时进行模拟，以验证选定的HDE。 EDA模拟器还具有模拟器接口; 和c）桥接RPLD和EDA模拟器的IPS控制器。 IPS控制器具有IPS执行程序，用于逐步验证和验证ESD。 IPS执行人员还包括一个协同仿真软件，用于共同和同时运行RPLD和EDA模拟器，并提供基于事件的同步方案，用于在RPLD和EDA模拟器之间交换交换矢量。

6. 发明授权

US08136065B2 Integrated prototyping system for validating an electronic system design 失效
标题翻译：用于验证电子系统设计的集成原型系统
公开(公告)号：US08136065B2
公开(公告)日：2012-03-13
申请号：US12110233
申请日：2008-04-25
申请人： Thomas B. Huang , Chioumin M. Chang
发明人： Thomas B. Huang , Chioumin M. Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator.
摘要翻译：提出了一种综合原型系统（IPS），用于验证和验证具有分层设计元素（HDE）的电子系统设计（ESD）。 IPS具有：a）具有仿真定时基的可编程逻辑器件（RPLD）和用于编程和模拟在确定交换向量时的HDE的RPLD接口。 RPLD还可切换地耦合到许多外部外围电子设备（PED），b）EDA模拟器，用于在交换向量的同时进行模拟，以验证选定的HDE。 EDA模拟器还具有模拟器接口; 和c）桥接RPLD和EDA模拟器的IPS控制器。 IPS控制器具有IPS执行程序，用于逐步验证和验证ESD。 IPS执行人员还包括一个协同仿真软件，用于共同和同时运行RPLD和EDA模拟器，并提供基于事件的同步方案，用于在RPLD和EDA模拟器之间交换交换矢量。

7. 发明授权

US07908576B2 Method of progressively prototyping and validating a customer's electronic system design 失效
标题翻译：逐步建立和验证客户电子系统设计的方法
公开(公告)号：US07908576B2
公开(公告)日：2011-03-15
申请号：US11953366
申请日：2007-12-10
申请人： Thomas B. Huang , Chioumin M. Chang
发明人： Thomas B. Huang , Chioumin M. Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： A method for prototyping and validating a customer's electronic system design (ESD) with design data is proposed. The design data is partitioned into hierarchical design elements (HDEs) plus their respective test benches. The ESD couples with customer's customer peripheral devices CPDs via their peripheral interface terminals PITs thus forming interconnected hierarchical system elements (HSEs) interacting with one another according to a functional validation specification. The HSEs form numerous system hierarchy levels (SHLs). The method includes: a) Providing a reprogrammable logic device (RPLD) with an RPLD-interface and programmable external interfaces PXIFs respectively connected to the PITs. b) Providing a simulation software tool. c) Disabling all PXIFs via RPLD-interface. (For each disabled PXIF, identifying HDEs connected to the PXIF and appending their test benches with stimuli and responses to form appended test benches. d) Progressively verifying and validating all HSEs against the functional validation specification following an upward movement along the SHLs.
摘要翻译：提出了一种利用设计数据原型设计和验证客户电子系统设计（ESD）的方法。设计数据被划分为层级设计元素（HDE）以及它们各自的测试台。 ESD通过其外围接口终端PIT与客户的客户外围设备CPD耦合，从而形成根据功能验证规范彼此交互的互连的分层系统元件（HSE）。 HSE形成许多系统层次结构（SHL）。该方法包括：a）提供具有分别连接到PIT的RPLD接口和可编程外部接口PXIF的可编程逻辑器件（RPLD）。 b）提供仿真软件工具。 c）通过RPLD接口禁用所有PXIF。（对于每个禁用的PXIF，识别连接到PXIF的HDE并附加刺激和响应的测试台，以形成附加的测试台。d）沿着SHL向上移动，逐步验证和验证所有HSE与功能验证规范。

8. 发明申请

US20090150838A1 METHOD OF PROGRESSIVELY PROTOTYPING AND VALIDATING A CUSTOMER'S ELECTRONIC SYSTEM DESIGN 失效
标题翻译：客户电子系统设计的进步原理和验证方法
公开(公告)号：US20090150838A1
公开(公告)日：2009-06-11
申请号：US11953366
申请日：2007-12-10
申请人： Thomas B. Huang , Chioumin M. Chang
发明人： Thomas B. Huang , Chioumin M. Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： A method for prototyping and validating a customer's electronic system design (ESD) with design data is proposed. The design data is partitioned into hierarchical design elements (HDEs) plus their respective test benches. The ESD couples with customer's customer peripheral devices CPDs via their peripheral interface terminals PITs thus forming interconnected hierarchical system elements (HSEs) interacting with one another according to a functional validation specification. The HSEs form numerous system hierarchy levels (SHLs). The method includes: a) Providing a reprogrammable logic device (RPLD) with an RPLD-interface and programmable external interfaces PXIFs respectively connected to the PITs. b) Providing a simulation software tool. c) Disabling all PXIFs via RPLD-interface. (For each disabled PXIF, identifying HDEs connected to the PXIF and appending their test benches with stimuli and responses to form appended test benches. d) Progressively verifying and validating all HSEs against the functional validation specification following an upward movement along the SHLs.
摘要翻译：提出了一种利用设计数据原型设计和验证客户电子系统设计（ESD）的方法。设计数据被划分为层级设计元素（HDE）以及它们各自的测试台。 ESD通过其外围接口终端PIT与客户的客户外围设备CPD耦合，从而形成根据功能验证规范彼此交互的互连的分层系统元件（HSE）。 HSE形成许多系统层次结构（SHL）。该方法包括：a）提供具有分别连接到PIT的RPLD接口和可编程外部接口PXIF的可编程逻辑器件（RPLD）。 b）提供仿真软件工具。 c）通过RPLD接口禁用所有PXIF。（对于每个禁用的PXIF，识别连接到PXIF的HDE并附加刺激和响应的测试台，以形成附加的测试台。d）沿着SHL向上移动，逐步验证和验证所有HSE与功能验证规范。

9. 发明授权

US5475830A Structure and method for providing a reconfigurable emulation circuit without hold time violations 失效
标题翻译：用于提供可重新配置的仿真电路的结构和方法，而不会发生持续时间违规
公开(公告)号：US5475830A
公开(公告)日：1995-12-12
申请号：US829181
申请日：1992-01-31
申请人： Nang-Ping Chen , Robert J. Ko , Jeong-Tyng Li , Thomas B. Huang , Ming-Yang Wang
发明人： Nang-Ping Chen , Robert J. Ko , Jeong-Tyng Li , Thomas B. Huang , Ming-Yang Wang
IPC分类号： G06F1/10 , A21B1/24 , F24C15/32 , G06F1/12 , G06F11/26 , G06F17/50 , H01L21/82 , H03K19/177 , G06F9/455
CPC分类号： A21B1/245 , G06F17/5027 , G06F17/5054
摘要： A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
摘要翻译：一种用于将集成电路设计实现为多个时钟和非锁定的可再编程逻辑电路的方法和结构。软件结构分析目标逻辑电路，形成集群，分割集成电路设计，并将分区实现为时钟和未锁定的可编程逻辑电路，以防止保持时间违规伪像。

10. 发明授权

US5649167A Methods for controlling timing in a logic emulation system 失效
标题翻译：用于控制逻辑仿真系统中的定时的方法
公开(公告)号：US5649167A
公开(公告)日：1997-07-15
申请号：US472531
申请日：1995-06-07
申请人： Nang-Ping Chen , Robert J. Ko , Jeong-Tyng Li , Thomas B. Huang , Ming-Yang Wang
发明人： Nang-Ping Chen , Robert J. Ko , Jeong-Tyng Li , Thomas B. Huang , Ming-Yang Wang
IPC分类号： G06F1/10 , A21B1/24 , F24C15/32 , G06F1/12 , G06F11/26 , G06F17/50 , H01L21/82 , H03K19/177 , H03K17/28
CPC分类号： A21B1/245 , G06F17/5027 , G06F17/5054
摘要： A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partitions the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
摘要翻译：一种用于将集成电路设计实现为多个时钟和非锁定的可再编程逻辑电路的方法和结构。软件结构分析目标逻辑电路，形成集群，分割集成电路设计，并将分区实现到时钟和未锁定的可编程逻辑电路中，以防止保持时间违规伪像。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式