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1. 发明授权

US06222227B1 Memory cell with self-aligned floating gate and separate select gate, and fabrication process 有权
标题翻译：具有自对准浮动栅极和分离选择栅极的存储单元，以及制造工艺
公开(公告)号：US06222227B1
公开(公告)日：2001-04-24
申请号：US09370557
申请日：1999-08-09
申请人： Chiou-Feng Chen
发明人： Chiou-Feng Chen
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/42328
摘要： Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the source and drain regions of the stack transistor. The memory cell is fabricated by forming a poly-1 layer and an overlying dielectric film on a substrate in areas in which the stack transistors are to be formed, forming a poly-2 layer over the dielectric film and over areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form control gates for the stack transistors and select gates for the select transistors, removing the poly-1 layer and the dielectric film to form floating gates in areas which are not covered by the control gates, and forming source and drain regions in the substrate. The floating gates are aligned with active areas in the substrate by forming isolation oxide regions which extend above the substrate at the edges of the active areas, and forming the floating gates on the sides of the isolation oxide regions in alignment with the edges of the active areas.
摘要翻译：具有浮动栅极的存储单元，其具有横向边缘，其直接对准在衬底中的有源区域的边缘上方，位于浮置栅极正上方的控制栅极和与控制栅极横向间隔开的选择栅极。浮动栅极具有底壁和侧壁，其以电容耦合关系面对控制栅极的相应壁，侧壁的高度为底壁宽度的80至160％。在一些实施例中，浮动栅极比上覆的控制栅极宽，并且具有覆盖堆叠晶体管的源极和漏极区域的突出部分。通过在要形成堆叠晶体管的区域中在衬底上形成多晶硅层和覆盖电介质膜来制造存储器单元，在电介质膜上形成多晶硅层，并在基底的区域要形成选择晶体管，对多晶硅层进行构图以形成堆叠晶体管的控制栅极和用于选择晶体管的选择栅极，去除多晶硅层和电介质膜，以在未被覆盖的区域中形成浮动栅极并且在衬底中形成源区和漏区。浮置栅极通过在有源区域的边缘处形成在衬底上方延伸的隔离氧化物区域而与衬底中的有源区域对准，并且在隔离氧化物区域的侧面上形成浮动栅极以与活性区域的边缘对准地区

2. 发明授权

US6091104A Flash memory cell with self-aligned gates and fabrication process 有权
标题翻译：具有自对准栅极和制造工艺的闪存单元
公开(公告)号：US6091104A
公开(公告)日：2000-07-18
申请号：US275670
申请日：1999-03-24
申请人： Chiou-Feng Chen
发明人： Chiou-Feng Chen
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L29/42328 , H01L29/7883
摘要： Nonvolatile memory cell and process in which a control gate or a thick dielectric film is used as a mask in the formation of a floating gate and also as a step in the formation and alignment of a select gate. The floating gate is relatively thin and has a side wall with a rounded curvature which, in some embodiments, serves as a tunneling window for electrons migrating to the select gate during erase operations. In other embodiments, the gate oxide beneath the floating gate is relatively thin, and the electrons tunnel through the gate oxide to the source region in the substrate below.
摘要翻译：非易失性存储单元和其中使用控制栅极或厚介电膜作为形成浮置栅极的掩模的工艺以及选择栅极的形成和对准中的步骤。浮动栅极相对较薄并且具有圆形曲率的侧壁，在一些实施例中，该侧壁用作在擦除操作期间迁移到选择栅极的电子的隧道窗口。在其他实施例中，浮置栅极下方的栅极氧化物相对较薄，并且电子通过栅极氧化物穿过下面的衬底中的源极区域。

3. 发明申请

US20060068529A1 Self-aligned split-gate NAND flash memory and fabrication process 有权
公开(公告)号：US20060068529A1
公开(公告)日：2006-03-30
申请号：US11281182
申请日：2005-11-16
申请人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： H01L21/8232
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

4. 发明申请

US20050145923A1 NAND flash memory with enhanced program and erase performance, and fabrication process 审中-公开
标题翻译： NAND闪存具有增强的编程和擦除性能，以及制作工艺
公开(公告)号：US20050145923A1
公开(公告)日：2005-07-07
申请号：US10753103
申请日：2004-01-06
申请人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
发明人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
IPC分类号： G11C16/04 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： NAND flash memory cell array and fabrication process in which control gates and floating gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other and
摘要翻译： NAND闪速存储器单元阵列和制造工艺，其中控制栅极和浮置栅极成对地堆叠成排列在位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。每个堆叠对中的门彼此自对齐，并且时，文本丢失或难以辨认

5. 发明授权

US06503785B2 Flash memory cell with contactless bit line, and process of fabrication 有权
公开(公告)号：US06503785B2
公开(公告)日：2003-01-07
申请号：US09862078
申请日：2001-05-21
申请人： Chiou-Feng Chen
发明人： Chiou-Feng Chen
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/11524 , H01L29/7885
摘要： Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

6. 发明授权

US07718488B2 Process of fabricating flash memory with enhanced program and erase coupling 有权
标题翻译：使用增强的编程和擦除耦合制造闪存的过程
公开(公告)号：US07718488B2
公开(公告)日：2010-05-18
申请号：US11380595
申请日：2006-04-27
申请人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
发明人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠通过在单元格行的末端的选择门。浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

7. 发明申请

US20060203552A1 Process of Fabricating Flash Memory with Enhanced Program and Erase Coupling 有权
标题翻译：使用增强的程序和擦除耦合制造闪存的过程
公开(公告)号：US20060203552A1
公开(公告)日：2006-09-14
申请号：US11380595
申请日：2006-04-27
申请人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
发明人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠通过在单元格行的末端的选择门。浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

8. 发明申请

US20050207225A1 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US20050207225A1
公开(公告)日：2005-09-22
申请号：US10803183
申请日：2004-03-17
申请人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： G11C16/00 , G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位排列源扩散。擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合其他大门。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

9. 发明申请

US20050207199A1 Flash memory with enhanced program and erase coupling and process of fabricating the same 有权
标题翻译：具有增强的编程和擦除耦合的闪存以及其制造过程
公开(公告)号：US20050207199A1
公开(公告)日：2005-09-22
申请号：US10802253
申请日：2004-03-17
申请人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
发明人： Chiou-Feng Chen , Prateep Tuntasood , Der-Tsyr Fan
IPC分类号： G11C5/02 , G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠通过在单元格行的末端的选择门。浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

10. 发明授权

US07217621B2 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US07217621B2
公开(公告)日：2007-05-15
申请号：US11281182
申请日：2005-11-16
申请人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： H01L21/336
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位排列源扩散。擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合其他大门。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

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