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1. 发明授权

US08345504B2 Data-aware dynamic supply random access memory 有权
标题翻译：数据感知动态供应随机存取存储器
公开(公告)号：US08345504B2
公开(公告)日：2013-01-01
申请号：US13009240
申请日：2011-01-19
申请人： Ching-Te Chuang , Hao-I Yang , Yi-Wei Lin , Wei Hwang , Wei-Chiang Shih , Chia-Cheng Chen
发明人： Ching-Te Chuang , Hao-I Yang , Yi-Wei Lin , Wei Hwang , Wei-Chiang Shih , Chia-Cheng Chen
IPC分类号： G11C11/40
CPC分类号： G11C11/413 , G11C11/412
摘要： A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
摘要翻译：提供具有多个单元的随机存取存储器（RAM）。在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。每个电池有两个逆变器; 电源控制器有两个电源开关。对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

2. 发明申请

US20120044779A1 DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY 有权
标题翻译：数据备注动态供应随机存取存储器
公开(公告)号：US20120044779A1
公开(公告)日：2012-02-23
申请号：US13009240
申请日：2011-01-19
申请人： Ching-Te Chuang , Hao-I Yang , Yi-Wei Lin , Wei Hwang , Wei-Chiang Shih , Chia-Cheng Chen
发明人： Ching-Te Chuang , Hao-I Yang , Yi-Wei Lin , Wei Hwang , Wei-Chiang Shih , Chia-Cheng Chen
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C11/412
摘要： A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
摘要翻译：提供具有多个单元的随机存取存储器（RAM）。在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。每个电池有两个逆变器; 电源控制器有两个电源开关。对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

3. 发明授权

US08320164B2 Static random access memory with data controlled power supply 有权
标题翻译：具有数据控制电源的静态随机存取存储器
公开(公告)号：US08320164B2
公开(公告)日：2012-11-27
申请号：US12985289
申请日：2011-01-05
申请人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Yung-Wei Lin , Chien-Yu Lu , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Chia-Cheng Chen , Wei-Chiang Shih
发明人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Yung-Wei Lin , Chien-Yu Lu , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Chia-Cheng Chen , Wei-Chiang Shih
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
摘要翻译：一种具有数据控制电源的静态随机存取存储器，其包括存储单元电路和至少一个写辅助电路，用于根据要写入存储单元电路的数据向存储单元电路供电。

4. 发明授权

US08804445B2 Oscillato based on a 6T SRAM for measuring the bias temperature instability 有权
标题翻译： Oscillato基于6T SRAM用于测量偏置温度不稳定性
公开(公告)号：US08804445B2
公开(公告)日：2014-08-12
申请号：US13484648
申请日：2012-05-31
申请人： Ching-Te Chuang , Shyh-Jye Jou , Wei Hwang , Ming-Chien Tsai , Yi-Wei Lin , Hao-I Yang , Ming-Hsien Tu , Wei-Chiang Shih , Nan-Chun Lien , Kuen-Di Lee
发明人： Ching-Te Chuang , Shyh-Jye Jou , Wei Hwang , Ming-Chien Tsai , Yi-Wei Lin , Hao-I Yang , Ming-Hsien Tu , Wei-Chiang Shih , Nan-Chun Lien , Kuen-Di Lee
IPC分类号： G11C7/04 , G11C29/12
CPC分类号： G11C29/12015 , G11C7/04 , G11C11/41 , G11C11/417 , G11C29/50 , G11C2029/5002 , H03K3/0315
摘要： The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.
摘要翻译：本发明提供一种基于用于测量偏压温度不稳定性的6T SRAM的振荡器。振荡器包括第一控制单元，第一反相器，第二控制单元和第二反相器。第一控制单元与第一逆变器耦合。第二控制单元与第二逆变器耦合。第一控制单元和第二控制单元用于分别选择，偏置和连接第一反相器和第二反相器，使得可以分别测量SRAM的NBTI和PBTI，并且实时稳定性可以立即监视SRAM。

5. 发明申请

US20130222071A1 Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability 有权
标题翻译：基于6T SRAM的振荡器，用于测量偏置温度不稳定性
公开(公告)号：US20130222071A1
公开(公告)日：2013-08-29
申请号：US13484648
申请日：2012-05-31
申请人： Ching-Te Chuang , Shyh-Jye Jou , Wei Hwang , Ming-Chien Tsai , Yi-Wei Lin , Hao-I Yang , Ming-Hsien Tu , Wei-Chiang Shih , Nan-Chun Lien , Kuen-Di Lee
发明人： Ching-Te Chuang , Shyh-Jye Jou , Wei Hwang , Ming-Chien Tsai , Yi-Wei Lin , Hao-I Yang , Ming-Hsien Tu , Wei-Chiang Shih , Nan-Chun Lien , Kuen-Di Lee
IPC分类号： H03K3/36
CPC分类号： G11C29/12015 , G11C7/04 , G11C11/41 , G11C11/417 , G11C29/50 , G11C2029/5002 , H03K3/0315
摘要： The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.
摘要翻译：本发明提供一种基于用于测量偏压温度不稳定性的6T SRAM的振荡器。振荡器包括第一控制单元，第一反相器，第二控制单元和第二反相器。第一控制单元与第一逆变器耦合。第二控制单元与第二逆变器耦合。第一控制单元和第二控制单元用于分别选择，偏置和连接第一反相器和第二反相器，使得可以分别测量SRAM的NBTI和PBTI，并且实时稳定性可以立即监视SRAM。

6. 发明授权

US08659936B2 Low power static random access memory 有权
标题翻译：低功率静态随机存取存储器
公开(公告)号：US08659936B2
公开(公告)日：2014-02-25
申请号：US12979345
申请日：2010-12-28
申请人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Wei Hwang , Chia-Cheng Chen , Wei-Chiang Shih
发明人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Wei Hwang , Chia-Cheng Chen , Wei-Chiang Shih
IPC分类号： G11C11/21
CPC分类号： G11C11/417 , G11C11/413
摘要： A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.
摘要翻译：在待机模式和写入模式下，将存储单元阵列保持在低电压状态的SRAM，并在读取模式下将存储单元阵列电源电压提高到高电平。一种SRAM，包括：至少一个存储单元电路，包括具有至少两个反相器的锁存电路，并且包括用于接收电力的两个电力接收端子; 以及供电电路，用于向存储单元电路提供电力，使得当数据被写入锁存电路时，锁存电路的电力接收端的电压低于预定的电压电平。在一个实施例中，存储单元电路包括多个数据访问终端，并且数据访问终端分别由至少两个传输晶体管开关器件控制。

7. 发明申请

US20120008449A1 LOW POWER STATIC RANDOM ACCESS MEMORY 有权
标题翻译：低功率静态随机存取存储器
公开(公告)号：US20120008449A1
公开(公告)日：2012-01-12
申请号：US12979345
申请日：2010-12-28
申请人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Wei Hwang , Chia-Cheng Chen , Wei-Chiang Shih
发明人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Wei Hwang , Chia-Cheng Chen , Wei-Chiang Shih
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C11/413
摘要： A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.
摘要翻译：在待机模式和写入模式下，将存储单元阵列保持在低电压状态的SRAM，并在读取模式下将存储单元阵列电源电压提高到高电平。一种SRAM，包括：至少一个存储单元电路，包括具有至少两个反相器的锁存电路，并且包括用于接收电力的两个电力接收端子; 以及供电电路，用于向存储单元电路提供电力，使得当数据被写入锁存电路时，锁存电路的电力接收端的电压低于预定的电压电平。在一个实施例中，存储单元电路包括多个数据访问终端，并且数据访问终端分别由至少两个传输晶体管开关器件控制。

8. 发明申请

US20120008377A1 STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY 有权
标题翻译：具有数据控制电源的静态随机存取存储器
公开(公告)号：US20120008377A1
公开(公告)日：2012-01-12
申请号：US12985289
申请日：2011-01-05
申请人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Yung-Wei Lin , Chien-Yu Lu , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Chia-Cheng Chen , Wei-Chiang Shih
发明人： Ching-Te Chuang , Hao-I Yang , Mao-Chih Hsia , Yung-Wei Lin , Chien-Yu Lu , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Chia-Cheng Chen , Wei-Chiang Shih
IPC分类号： G11C11/40 , G11C5/14
CPC分类号： G11C11/419
摘要： A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
摘要翻译：一种具有数据控制电源的静态随机存取存储器，其包括存储单元电路和至少一个写辅助电路，用于根据要写入存储单元电路的数据向存储单元电路供电。

9. 发明申请

US20130223136A1 SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor 审中-公开
标题翻译：基于6晶体管结构的SRAM，包括第一反相器，第二反相器，第一通过栅极晶体管和第二通过栅极晶体管
公开(公告)号：US20130223136A1
公开(公告)日：2013-08-29
申请号：US13484497
申请日：2012-05-31
申请人： Ching-Te CHUANG , Shyh-Jye Jou , Wei Hwang , Yi-Wei Lin , Ming-Chien Tsai , Hao-I Yang , Ming-Hsien Tu , Wei-Chiang Shih , Nan-Chun Lien , Kuen-Di Lee
发明人： Ching-Te CHUANG , Shyh-Jye Jou , Wei Hwang , Yi-Wei Lin , Ming-Chien Tsai , Hao-I Yang , Ming-Hsien Tu , Wei-Chiang Shih , Nan-Chun Lien , Kuen-Di Lee
IPC分类号： G11C11/40
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5002
摘要： The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.
摘要翻译：本发明提供一种包括第一反相器，第二反相器，第一通过栅极晶体管和第二通过栅极晶体管的6T SRAM。第一反相器zs是第一上拉晶体管和第一下拉晶体管。第二反相器包括第二上拉晶体管和第二下拉晶体管。第二上拉晶体管的栅极与第二下拉晶体管的栅极耦合，并且第二上拉晶体管的漏极与第二下拉晶体管的漏极耦合。 SRAM可以通过控制第一位线，第二位线，GND，第一字线和电压源来测量跳闸电压，读取干扰电压和写入裕度，而不改变SRAM的物理参数。

10. 发明授权

US08385149B2 Gate oxide breakdown-withstanding power switch structure 有权
标题翻译：栅极氧化物击穿电源开关结构
公开(公告)号：US08385149B2
公开(公告)日：2013-02-26
申请号：US13075682
申请日：2011-03-30
申请人： Hao-I Yang , Ching-Te Chuang , Wei Hwang
发明人： Hao-I Yang , Ching-Te Chuang , Wei Hwang
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.
摘要翻译：本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

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