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1. 发明授权

US08440511B1 Method for manufacturing multi-gate transistor device 有权
标题翻译：多栅极晶体管器件制造方法
公开(公告)号：US08440511B1
公开(公告)日：2013-05-14
申请号：US13298264
申请日：2011-11-16
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/306 , H01L29/66795 , H01L29/7854
摘要： A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
摘要翻译：一种用于制造多栅极晶体管器件的方法包括：提供具有图案化半导体层的半导体衬底和在其上依次形成的图案化硬掩模，去除图案化的硬掩模，进行热处理以使处理温度低于 800℃，并顺序地形成覆盖半导体衬底上的图案化半导体层的一部分的栅极电介质层和栅极层。

2. 发明申请

US20130122698A1 METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE 有权
标题翻译：制造多栅极晶体管器件的方法
公开(公告)号：US20130122698A1
公开(公告)日：2013-05-16
申请号：US13298264
申请日：2011-11-16
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Min-Ying Hsu , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L21/28
CPC分类号： H01L21/306 , H01L29/66795 , H01L29/7854
摘要： A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
摘要翻译：一种用于制造多栅极晶体管器件的方法包括：提供具有图案化半导体层的半导体衬底和在其上依次形成的图案化硬掩模，去除图案化的硬掩模，进行热处理以使处理温度低于 800℃，并顺序地形成覆盖半导体衬底上的图案化半导体层的一部分的栅极电介质层和栅极层。

3. 发明申请

US20130052778A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130052778A1
公开(公告)日：2013-02-28
申请号：US13216259
申请日：2011-08-24
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66628
摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
摘要翻译：半导体工艺包括以下步骤。提供基板。在基板上形成至少一个鳍状结构。在基板上形成氧化层，而不形成鳍状结构。形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

4. 发明授权

US08674433B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08674433B2
公开(公告)日：2014-03-18
申请号：US13216259
申请日：2011-08-24
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L29/66628
摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
摘要翻译：半导体工艺包括以下步骤。提供基板。在基板上形成至少一个鳍状结构。在基板上形成氧化层，而不形成鳍状结构。形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

5. 发明授权

US08796695B2 Multi-gate field-effect transistor and process thereof 有权
标题翻译：多栅极场效应晶体管及其工艺
公开(公告)号：US08796695B2
公开(公告)日：2014-08-05
申请号：US13530127
申请日：2012-06-22
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L29/772
CPC分类号： H01L29/66795 , H01L29/1054 , H01L29/66484 , H01L29/785
摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
摘要翻译：多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。鳍状结构位于基板上。栅极结构设置在鳍状结构和衬底的一部分上。外延结构位于栅极结构旁边的鳍状结构上。梯度盖层位于每个外延结构上。梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

6. 发明申请

US20130341638A1 MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF 有权
标题翻译：多栅极场效应晶体管及其工艺
公开(公告)号：US20130341638A1
公开(公告)日：2013-12-26
申请号：US13530127
申请日：2012-06-22
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L29/772 , H01L21/20 , H01L29/161
CPC分类号： H01L29/66795 , H01L29/1054 , H01L29/66484 , H01L29/785
摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
摘要翻译：多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。鳍状结构位于基板上。栅极结构设置在鳍状结构和衬底的一部分上。外延结构位于栅极结构旁边的鳍状结构上。梯度盖层位于每个外延结构上。梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

7. 发明申请

US20090039428A1 FABRICATING METHOD FOR SILICON ON INSULATOR AND STRUCTURE THEREOF 审中-公开
标题翻译：绝缘子上的硅及其结构的制造方法
公开(公告)号：US20090039428A1
公开(公告)日：2009-02-12
申请号：US12053679
申请日：2008-03-24
申请人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
发明人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L21/76245
摘要： A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.
摘要翻译：公开了一种绝缘体硅的制造方法，其制造方法包括：剥离每个沟槽的底表面上的氧化物和氮化物，通过阳极氧化处理在衬底的部分上形成多孔硅，旋涂介电材料填充沟槽并执行热处理以将多孔硅转化为绝缘层。

8. 发明申请

US20080316674A1 Capacitors and methods for fabricating the same 审中-公开
标题翻译：电容器及其制造方法
公开(公告)号：US20080316674A1
公开(公告)日：2008-12-25
申请号：US12000145
申请日：2007-12-10
申请人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
发明人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
IPC分类号： H01G4/06 , H01G9/00
CPC分类号： H01L28/91 , H01G4/252 , H01G4/33 , H01L27/10852
摘要： Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.
摘要翻译：提供了电容器及其制造方法。电容器的示例性实施例包括电介质层和其上的第一导电层。支撑肋嵌入在第一导电层中并且沿着第一方向延伸。第二导电层被嵌入在第一导电层中并且沿着与第一方向垂直的第二方向延伸，其中第二导电层的一部分跨过支撑肋形成并且在结构上由支撑肋支撑。在第一和第二导电层之间形成电容器层，以使第一和第二导电层电绝缘。

9. 发明授权

US07919384B2 Method of making planar-type bottom electrode for semiconductor device 有权
标题翻译：制造半导体器件的平面型底电极的方法
公开(公告)号：US07919384B2
公开(公告)日：2011-04-05
申请号：US12050649
申请日：2008-03-18
申请人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
发明人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
IPC分类号： H01L21/20
CPC分类号： H01L28/91
摘要： A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.
摘要翻译：公开了制造半导体器件的平面型底电极的方法。在基板上形成牺牲层结构。在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。绝缘层分别分开彼此分离的底部电极层。最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

10. 发明申请

US20090023268A1 ISOLATION METHOD OF ACTIVE AREA FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的主动区隔离方法
公开(公告)号：US20090023268A1
公开(公告)日：2009-01-22
申请号：US12108306
申请日：2008-04-23
申请人： Hsiao-Che WU , Ming-Yen Li , Wen-Li Tsai
发明人： Hsiao-Che WU , Ming-Yen Li , Wen-Li Tsai
IPC分类号： H01L21/762
CPC分类号： H01L21/76205 , H01L21/823878
摘要： An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas.
摘要翻译：用于半导体的有源区的隔离方法在衬底中形成隔离的有源区。衬底是p型硅衬底。衬底氧化层形成在衬底上。在衬垫氧化物层上形成图案化牺牲层和上掩模层，其中上掩模层形成在衬底的隔离区上。在图案化的牺牲层和上掩模层之间形成间隙。进行注入工艺以通过间隙将离子掺杂到衬底中，其形成围绕有源区的n型势垒。最后，剥离图案化的牺牲层，并且使用阳极氧化工艺将p型体硅转化为多孔硅。然后，进行氧化处理以氧化多孔硅以形成活性区的二氧化硅隔离区。

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