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1. 发明授权

US08448100B1 Tool and method for eliminating multi-patterning conflicts 有权
标题翻译：消除多图案化冲突的工具和方法
公开(公告)号：US08448100B1
公开(公告)日：2013-05-21
申请号：US13444158
申请日：2012-04-11
申请人： Hung Lung Lin , Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Chin-Hsiung Hsu , Huang-Yu Chen , Yi-Chuin Tsai , Yuan-Te Hou , Chung-Hsing Wang
发明人： Hung Lung Lin , Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Chin-Hsiung Hsu , Huang-Yu Chen , Yi-Chuin Tsai , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.
摘要翻译：计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。

2. 发明授权

US08601409B1 Compression method and system for use with multi-patterning 有权
公开(公告)号：US08601409B1
公开(公告)日：2013-12-03
申请号：US13547107
申请日：2012-07-12
申请人： Huang-Yu Chen , Chin-Hsiung Hsu , Wen-Hao Chen , Chung-Hsing Wang
发明人： Huang-Yu Chen , Chin-Hsiung Hsu , Wen-Hao Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/70 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

3. 发明授权

US08539396B2 Stitch and trim methods for double patterning compliant standard cell design 有权
标题翻译：针对符合标准单元设计的双图案的针迹和修剪方法
公开(公告)号：US08539396B2
公开(公告)日：2013-09-17
申请号：US13415997
申请日：2012-03-09
申请人： Chin-Hsiung Hsu , Huang-Yu Chen , Chung-Hsing Wang
发明人： Chin-Hsiung Hsu , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5072 , G06F2217/78
摘要： A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.
摘要翻译：公开了一种用于产生双重图案化的集成电路布局的方法。该方法允许在光刻期间将图案分配给不同的掩模并缝合在一起。该方法还允许在处理之后去除图案的部分。

4. 发明授权

US08745556B2 Layout method and system for multi-patterning integrated circuits 有权
标题翻译：多图案集成电路的布局方法和系统
公开(公告)号：US08745556B2
公开(公告)日：2014-06-03
申请号：US13535705
申请日：2012-06-28
申请人： Huang-Yu Chen , Tsong-Hua Ou , Ken-Hsien Hsieh , Chin-Hsiung Hsu
发明人： Huang-Yu Chen , Tsong-Hua Ou , Ken-Hsien Hsieh , Chin-Hsiung Hsu
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/12
摘要： A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.
摘要翻译：一种方法将作为独立节点的任何节点表示在不包括在布局的任何其它奇数循环中的IC层的区域的布局的任何奇数循环中的电路图案。该层将具有使用至少三个光掩模进行图案化的多个电路图案。该方法将安全独立节点识别为距离布局的另一个奇数循环中任何其他独立节点不超过阈值距离的任何独立节点。布局被修改，如果布局中的电路图案包括没有任何安全独立节点的任何奇数循环，使得在修改之后，每个奇数循环至少有一个安全独立节点。

5. 发明申请

US20110004858A1 METHOD FOR CONCURRENT MIGRATION AND DECOMPOSITION OF INTEGRATED CIRCUIT LAYOUT 审中-公开
标题翻译：用于集成电路布局的同时移动和分解的方法
公开(公告)号：US20110004858A1
公开(公告)日：2011-01-06
申请号：US12550484
申请日：2009-08-31
申请人： Yao-Wen Chang , Chin-Hsiung Hsu
发明人： Yao-Wen Chang , Chin-Hsiung Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for concurrent migration and decomposition of an integrated circuit layout applicable to double patterning lithography techniques is provided. The method includes cutting a sub-pattern of an initial pattern to configure a potentially conflicting pattern having separate or cutting sections; removing odd cycles in the potential conflicting pattern so as to cut the separate or cutting sections; configuring the double patterning constraint based upon corresponding location relations between each and adjacent cut sections; and assigning a first color layer or a second color layer to the cut sections according to the double patterning constraint to obtain a final layout pattern. Therefore, disadvantageous factors and patterning conflicts caused by separate processes as encountered in the prior art are avoided.
摘要翻译：提供了一种用于并行迁移和分解适用于双重图案化光刻技术的集成电路布局的方法。该方法包括切割初始图案的子图案以配置具有分离或切割部分的潜在冲突图案; 去除潜在的冲突图案中的奇数循环，从而切割单独或切割部分; 基于每个相邻切割部分之间的相应位置关系来配置双重图案化约束; 以及根据双重图案化约束将切割部分分配第一颜色层或第二颜色层以获得最终布局图案。因此，避免了由现有技术中遇到的单独处理引起的不利因素和图案化冲突。

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