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1. 发明授权

US08822284B2 Method for fabricating FinFETs and semiconductor structure fabricated using the method 有权
标题翻译：使用该方法制造FinFET和半导体结构的方法
公开(公告)号：US08822284B2
公开(公告)日：2014-09-02
申请号：US13370231
申请日：2012-02-09
申请人： Chin-Fu Lin , Chin-Cheng Chien , Chun-Yuan Wu , Teng-Chun Tsai , Chih-Chien Liu
发明人： Chin-Fu Lin , Chin-Cheng Chien , Chun-Yuan Wu , Teng-Chun Tsai , Chih-Chien Liu
IPC分类号： H01L29/06 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L21/02 , H01L21/3115 , H01L21/311 , H01L21/318 , H01L21/314
CPC分类号： H01L29/785 , H01L21/02381 , H01L21/02532 , H01L21/02636 , H01L21/31111 , H01L21/31116 , H01L21/3115 , H01L21/3141 , H01L21/3185 , H01L21/764 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10879 , H01L29/1095 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795
摘要： A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
摘要翻译：描述了制造FinFET的方法。图案化半导体衬底以形成奇数鳍片。间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。然后在间隔件之间的基板上均匀形成翅片。还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

2. 发明授权

US08647941B2 Method of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08647941B2
公开(公告)日：2014-02-11
申请号：US13211319
申请日：2011-08-17
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L21/8238
CPC分类号： H01L29/7846 , H01L21/76283 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
摘要翻译：形成半导体器件的方法包括以下步骤。提供具有第一应变硅层的半导体衬底。然后，形成诸如浅沟槽隔离（STI）的绝缘区域，其中绝缘区域的深度基本上大于第一应变硅层的深度。随后，去除第一应变硅层，形成第二应变硅层以代替第一应变硅层。

3. 发明授权

US08497198B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08497198B2
公开(公告)日：2013-07-30
申请号：US13243485
申请日：2011-09-23
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L21/4763 , H01L21/3205 , H01L21/336
CPC分类号： H01L29/66795
摘要： A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
摘要翻译：半导体工艺描述如下。在基板上形成多个虚设图案。在基板上共形形成掩模材料层，以覆盖虚设图案。掩模材料层具有与虚拟图案不同的蚀刻速率。除去掩模材料层的一部分，以便在每个虚设图案的各个侧壁上形成掩模层。掩模层的上表面和每个虚拟图案的上表面基本上共面。虚拟图案被去除。使用掩模层作为掩模去除衬底的一部分，以便形成多个翅片结构和交替布置在衬底中的多个沟槽。去除掩模层。

4. 发明申请

US20130045579A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20130045579A1
公开(公告)日：2013-02-21
申请号：US13211319
申请日：2011-08-17
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L21/76283 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
摘要翻译：形成半导体器件的方法包括以下步骤。提供具有第一应变硅层的半导体衬底。然后，形成诸如浅沟槽隔离（STI）的绝缘区域，其中绝缘区域的深度基本上大于第一应变硅层的深度。随后，去除第一应变硅层，形成第二应变硅层以代替第一应变硅层。

5. 发明申请

US20130001707A1 FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： MOS晶体管的制造方法，Fin场效应晶体管及其制造方法
公开(公告)号：US20130001707A1
公开(公告)日：2013-01-03
申请号：US13174711
申请日：2011-06-30
申请人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L21/02332 , H01L29/512 , H01L29/66795 , H01L29/785
摘要： A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
摘要翻译： MOS晶体管的制造方法包括以下步骤。提供基板。在基板上形成栅介电层。进行包含氮等离子体和氦气的氮化处理，以对栅介质层进行氮化。还提供了鳍状场效应晶体管及其制造方法。

6. 发明授权

US08324118B2 Manufacturing method of metal gate structure 有权
标题翻译：金属门结构的制造方法
公开(公告)号：US08324118B2
公开(公告)日：2012-12-04
申请号：US13072795
申请日：2011-03-28
申请人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
发明人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
IPC分类号： H01L21/31
CPC分类号： H01L29/517 , H01L21/28185 , H01L29/513 , H01L29/66545
摘要： A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).
摘要翻译：金属栅极结构的制造方法包括提供具有形成在其上的至少第一金属氧化物层的基板，并将第一金属氧化物层的表面转移到第二金属氧化物层中。第一金属氧化物层包括第一金属（M1）的金属氧化物（M1Ox），第二金属氧化物层包括第一金属的金属氧化物（（M1M2Oy））和第二金属（M2）。

7. 发明申请

US20120241863A1 FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF 有权
标题翻译： FIN场效应晶体管结构及其制造工艺
公开(公告)号：US20120241863A1
公开(公告)日：2012-09-27
申请号：US13052338
申请日：2011-03-21
申请人： Teng-Chun TSAI , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
发明人： Teng-Chun TSAI , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78 , H01L29/66545 , H01L29/66795 , H01L29/7833
摘要： A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
摘要翻译：鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。高k金属栅极形成在基板和鳍状通道上。制造鳍式场效应晶体管结构的工艺包括以下步骤。首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。

8. 发明授权

US08609529B2 Fabrication method and structure of through silicon via 有权
标题翻译：通过硅通孔的制造方法和结构
公开(公告)号：US08609529B2
公开(公告)日：2013-12-17
申请号：US13363390
申请日：2012-02-01
申请人： Chin-Fu Lin , Chun-Yuan Wu , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien
发明人： Chin-Fu Lin , Chun-Yuan Wu , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien
IPC分类号： H01L21/4763
CPC分类号： H01L21/3085 , H01L21/3086 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
摘要翻译：一种制造贯穿硅通孔（TSV）结构的方法，其中在基板上形成图案化掩模，所述图案化掩模具有开口，在所述开口的侧壁上形成间隔物结构，并且所述通孔通过在形成间隔物结构之后通过开口蚀刻间隔物结构和基底而形成具有相对扩大的开口。 TSV结构，其中通孔具有开口部分和主体部分，所述开口部分是相对扩大的开口，并且具有开口尺寸大于下部开口尺寸的上部开口尺寸的锥形形状。

9. 发明申请

US20130207122A1 METHOD FOR FABRICATING FINFETS AND SEMICONDUCTOR STRUCTURE FABRICATED USING THE METHOD 有权
标题翻译：使用该方法制造FinFET和半导体结构的方法
公开(公告)号：US20130207122A1
公开(公告)日：2013-08-15
申请号：US13370231
申请日：2012-02-09
申请人： Chin-Fu Lin , Chin-Cheng Chien , Chun-Yuan Wu , Teng-Chun Tsai , Chih-Chien Liu
发明人： Chin-Fu Lin , Chin-Cheng Chien , Chun-Yuan Wu , Teng-Chun Tsai , Chih-Chien Liu
IPC分类号： H01L21/764 , H01L29/24
CPC分类号： H01L29/785 , H01L21/02381 , H01L21/02532 , H01L21/02636 , H01L21/31111 , H01L21/31116 , H01L21/3115 , H01L21/3141 , H01L21/3185 , H01L21/764 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10879 , H01L29/1095 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795
摘要： A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
摘要翻译：描述了制造FinFET的方法。图案化半导体衬底以形成奇数鳍片。间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。然后在间隔件之间的基板上均匀形成翅片。还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

10. 发明授权

US08441072B2 Non-planar semiconductor structure and fabrication method thereof 有权
标题翻译：非平面半导体结构及其制造方法
公开(公告)号：US08441072B2
公开(公告)日：2013-05-14
申请号：US13224344
申请日：2011-09-02
申请人： Shih-Hung Tsai , Chien-Ting Lin , Chin-Cheng Chien , Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chun-Yuan Wu
发明人： Shih-Hung Tsai , Chien-Ting Lin , Chin-Cheng Chien , Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chun-Yuan Wu
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/66795
摘要： A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
摘要翻译：非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。鳍状结构位于基底上。隔离结构位于鳍状结构之间，隔离结构具有含氮层。外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。还提供了用于形成半导体结构的非平面半导体工艺。

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