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1. 发明授权

US07106613B2 Memory module and a method of arranging a signal line of the same 失效
标题翻译：存储器模块及其配置信号线的方法
公开(公告)号：US07106613B2
公开(公告)日：2006-09-12
申请号：US11064671
申请日：2005-02-24
申请人： Chil-Nam Yoon , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Young-Jun Park , Il-Sung Yu
发明人： Chil-Nam Yoon , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Young-Jun Park , Il-Sung Yu
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.
摘要翻译：本发明公开了一种存储模块及其配置信号线的方法。布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

2. 发明申请

US20050185439A1 Memory module and a method of arranging a signal line of the same 失效
标题翻译：存储器模块及其配置信号线的方法
公开(公告)号：US20050185439A1
公开(公告)日：2005-08-25
申请号：US11064671
申请日：2005-02-24
申请人： Chil-Nam Yoon , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Young-Jun Park , Il-Sung Yu
发明人： Chil-Nam Yoon , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Young-Jun Park , Il-Sung Yu
IPC分类号： G06F12/00 , G11C5/06 , G11C11/401 , H05K1/18
CPC分类号： G11C5/063 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.
摘要翻译：本发明公开了一种存储模块及其配置信号线的方法。布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

3. 发明申请

US20050002241A1 Memory system with improved signal integrity 审中-公开
标题翻译：具有改善信号完整性的存储系统
公开(公告)号：US20050002241A1
公开(公告)日：2005-01-06
申请号：US10837610
申请日：2004-05-04
申请人： Sung-Joo Park , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Chil-Nam Yoon
发明人： Sung-Joo Park , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Chil-Nam Yoon
IPC分类号： G06F12/00 , G06F13/40 , G11C5/00 , G11C5/06
CPC分类号： G06F13/4086
摘要： A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.
摘要翻译：存储器系统包括存储器控制器，连接到存储器控制器的存储器总线以及沿着存储器总线连接的多个存储器模块，其中每个存储器模块包括多个存储器件。该系统还包括连接到存储器总线之间的存储器控制器和位于多个存储器模块中最靠近存储器控制器的存储器模块之间的虚拟存根或虚拟模块。虚拟短线或虚拟模块改善了至少与存储器控制器最接近的存储器模块的信号完整性。

4. 发明授权

US07652949B2 Memory module and register with minimized routing path 失效
标题翻译：内存模块和注册最小化路由路径
公开(公告)号：US07652949B2
公开(公告)日：2010-01-26
申请号：US11633353
申请日：2006-12-04
申请人： Chil-Nam Yoon , Young-Man Ahn , Young-Jun Park , Sung-Joo Park
发明人： Chil-Nam Yoon , Young-Man Ahn , Young-Jun Park , Sung-Joo Park
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G11C5/04 , G11C5/063
摘要： A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.
摘要翻译：存储器模块包括包括多个存储器件的第一存储器组，包括相对于第一存储器组中的存储器件的较少数量的存储器件的第二存储器组，配置成向第一存储器组件提供命令/地址信号的寄存器第一存储器组和延迟的命令/地址信号到第二存储器组，第一信号线，被配置为将命令/地址信号传送到第一存储器组;以及第二信号线，被配置为将延迟的命令/地址信号传送到第二内存组。

5. 发明申请

US20070127304A1 Memory module and register with minimized routing path 失效
标题翻译：内存模块和注册最小化路由路径
公开(公告)号：US20070127304A1
公开(公告)日：2007-06-07
申请号：US11633353
申请日：2006-12-04
申请人： Chil-Nam Yoon , Young-Man Ahn , Young-Jun Park , Sung-Joo Park
发明人： Chil-Nam Yoon , Young-Man Ahn , Young-Jun Park , Sung-Joo Park
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C5/04 , G11C5/063
摘要： A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.
摘要翻译：存储器模块包括包括多个存储器件的第一存储器组，包括相对于第一存储器组中的存储器件的较少数量的存储器件的第二存储器组，配置成向第一存储器组件提供命令/地址信号的寄存器第一存储器组和延迟的命令/地址信号到第二存储器组，第一信号线，被配置为将命令/地址信号传送到第一存储器组;以及第二信号线，被配置为将延迟的命令/地址信号传送到第二内存组。

6. 发明申请

US20060207788A1 Memory module and signal line arrangement method thereof 有权
标题翻译：存储模块及其信号线排列方法
公开(公告)号：US20060207788A1
公开(公告)日：2006-09-21
申请号：US11357500
申请日：2006-02-17
申请人： Chil-Nam Yoon , Kwang-Seop Kim , Do-Hyung Kim , Jae-Jun Lee , Ki-Hyun Ko
发明人： Chil-Nam Yoon , Kwang-Seop Kim , Do-Hyung Kim , Jae-Jun Lee , Ki-Hyun Ko
IPC分类号： H05K7/06
CPC分类号： H05K1/181 , G11C5/025 , G11C5/04 , H05K1/112 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , Y10T29/49128 , Y10T29/49155
摘要： In a memory module and a signal line arrangement method thereof, the memory module comprises: memory chips mounted on both sides of the module in a mirrored configuration; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sides in contact with same signal applying balls of the memory chips in the mirrored configuration, the PCB including a via at a location proximal to the same signal applying contact pad of one side of the PCB among the same signal applying contact pads arranged on both sides in the mirrored configuration, the via connecting an other side of the PCB to the one side of the PCB, and a contact junction connected to the same signal applying contact pad of the other side of the PCB, the contact junction being connected to the via of the other side of the PCB, and the via of the one side of the PCB being connected to the same signal applying contact pad of the one side of the PCB, the contact junction connected to a signal terminal from the other side of the PCB.
摘要翻译：在存储器模块及其信号线布置方法中，存储器模块包括：以镜像配置安装在模块两侧的存储器芯片; 以及具有相同信号的印刷电路板（PCB），其施加布置在两侧的接触焊盘，以与镜像配置中的存储器芯片的相同信号施加球接触，PCB包括位于相邻信号施加接触垫在布置在镜面配置两侧的相同信号施加接触垫中的PCB的一侧，通孔将PCB的另一侧连接到PCB的一侧，以及连接到相同信号的接触点施加接触 PCB的另一侧的焊盘，接触点连接到PCB的另一侧的通孔，并且PCB的一侧的通孔连接到施加与该PCB的一侧的接触焊盘相同的信号 PCB，接触点从PCB的另一侧连接到信号端子。

7. 发明授权

US07390973B2 Memory module and signal line arrangement method thereof 有权
标题翻译：存储模块及其信号线排列方法
公开(公告)号：US07390973B2
公开(公告)日：2008-06-24
申请号：US11357500
申请日：2006-02-17
申请人： Chil-Nam Yoon , Kwang-Seop Kim , Do-Hyung Kim , Jae-Jun Lee , Ki-Hyun Ko
发明人： Chil-Nam Yoon , Kwang-Seop Kim , Do-Hyung Kim , Jae-Jun Lee , Ki-Hyun Ko
IPC分类号： H05K1/16
CPC分类号： H05K1/181 , G11C5/025 , G11C5/04 , H05K1/112 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , Y10T29/49128 , Y10T29/49155
摘要： The pesent invention discloses a memory module and a signal line arrangement method thereof. The memory module includes memory chips mounted on both sidees in a mirror form; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sodes which same signal applying balls of the memory chips contact in the mirror form, wherein a via is formed at a location close to the same signal applying contact pad of one side among the same signal applying contact pads arranged on both sides in the mirror form, the via connecting the other side to the signal line of one side, and a signal transmitted from the other side is connected to a contact junction, the contact junction is connected to the same signal applying contact pad of the other side, the contact junction is connected to the via of the other side, and the via of one side is connected to the same signal applying contact pad of one side.
摘要翻译：本发明公开了一种存储模块及其信号线排列方法。存储器模块包括以镜子形式安装在两侧的存储器芯片; 以及具有相同信号的印刷电路板（PCB），其施加布置在两个信号线上的接触焊盘，所述存储器芯片的相同信号施加球以镜子形式接触，其中通孔形成在接近相同信号的位置处，施加接触焊盘在相同的信号中，以镜面形式设置在两侧的接触焊盘的一侧，将另一侧连接到一侧的信号线的通孔，并且从另一侧传输的信号连接到接触接点，接触接点连接到另一侧的相同信号施加接触焊盘，接触点连接到另一侧的通孔，并且一侧的通孔连接到施加一侧接触焊盘的相同信号。

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