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1. 发明授权

US09052332B2 Piezoresistive type Z-axis accelerometer 有权
标题翻译：压阻式Z轴加速度计
公开(公告)号：US09052332B2
公开(公告)日：2015-06-09
申请号：US13484681
申请日：2012-05-31
申请人： Chih-Wei Huang , Chieh-Pin Chang , Ja-Hao Chen , Chuan-Jane Chao , Ying-Zong Juang , Shyh-Chyi Wong , Yeong-Her Wang
发明人： Chih-Wei Huang , Chieh-Pin Chang , Ja-Hao Chen , Chuan-Jane Chao , Ying-Zong Juang , Shyh-Chyi Wong , Yeong-Her Wang
IPC分类号： G01P15/09 , G01P15/08 , G01P15/12
CPC分类号： G01P15/0802 , G01P15/123 , G01P2015/0837
摘要： A pizeoresistive type Z-axis accelerometer is provided, including a substrate; a plurality of anchors formed over the substrate; a plurality of cantilever beams, wherein the cantilever beams include a piezoresistive material; and a proof mass, wherein the proof mass is suspended over the substrate by respectively connecting the proof mass with the anchors, and the accelerometer senses a movement of the proof mass by the piezoresistive material.
摘要翻译：提供了一种包括基板的等离子体型Z轴加速度计，形成在所述基板上的多个锚固件; 多个悬臂梁，其中所述悬臂梁包括压阻材料; 以及证明物质，其中通过分别将证明物质与锚固件连接，将证明物料悬浮在基材上，并且加速度计通过压阻材料感测证明物质的移动。

2. 发明授权

US08904868B2 Sensing apparatus 有权
标题翻译：传感装置
公开(公告)号：US08904868B2
公开(公告)日：2014-12-09
申请号：US13458359
申请日：2012-04-27
申请人： Chih-Wei Huang , Chieh-Pin Chang , Ja-Hao Chen , Chuan-Jane Chao , Ying-Zong Juang , Shyh-Chyi Wong , Yeong-Her Wang
发明人： Chih-Wei Huang , Chieh-Pin Chang , Ja-Hao Chen , Chuan-Jane Chao , Ying-Zong Juang , Shyh-Chyi Wong , Yeong-Her Wang
IPC分类号： G01P15/125 , G01P15/08
CPC分类号： G01P15/125 , G01P2015/0814
摘要： A sensing apparatus includes an acceleration sensing unit, for measuring an acceleration applied to a proof mass, further including: a proof mass; a carrier signal source, for providing a carrier signal; a capacitive half-bridge, including a first and a second capacitor, wherein each capacitor is coupled to the proof mass and the carrier signal source, one with a positive electrode and the other one with a negative electrode, and the acceleration applied to the proof mass makes the carrier signal flow through the first and the second capacitor so that the first capacitor and the second capacitor respectively generates a first voltage and a second voltage variation which have opposite phases with each other; and an instrumentation amplifier, for receiving and amplifying the first voltage and the second voltage variation, whereby the magnitude and the direction of the acceleration applied to the proof mass is determined.
摘要翻译：感测装置包括加速度检测单元，用于测量施加到检验质量块的加速度，还包括：检验质量块; 载波信号源，用于提供载波信号; 包括第一和第二电容器的电容半桥，其中每个电容器耦合到检测质量块和载波信号源，一个具有正电极，另一个与负电极耦合，并且加速度应用于证明质量使载体信号流过第一和第二电容器，使得第一电容器和第二电容器分别产生彼此具有相反相位的第一电压和第二电压变化; 以及用于接收和放大第一电压和第二电压变化的仪表放大器，由此确定施加到检验质量块的加速度的大小和方向。

3. 发明授权

US08026767B2 Adaptive bias circuit and system thereof 有权
标题翻译：自适应偏置电路及其系统
公开(公告)号：US08026767B2
公开(公告)日：2011-09-27
申请号：US12545084
申请日：2009-08-21
申请人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
发明人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F1/0266 , H03F1/56 , H03F3/195 , H03F3/245 , H03F2200/108 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2200/555
摘要： An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.
摘要翻译：使用相对于功率电平提供更灵敏的自适应偏置电流的自适应偏置电路用于偏置电子电路。自适应偏置电路具有耦合到电源的第一晶体管，耦合到第一晶体管的电压偏置电路和偏置第一晶体管的电源，以及耦合到第一晶体管和电子电路的第一功率耦合模块，用于耦合输入信号功率的一部分到第一晶体管。第二晶体管耦合到第一晶体管和电源以增加自适应偏置电路的电流增益，并且第二电流耦合模块耦合到第二晶体管和电子电路以向电子电路提供自适应偏置电流。

4. 发明申请

US20110043287A1 ADAPTIVE BIAS CIRCUIT AND SYSTEM THEREOF 有权
标题翻译：自适应偏置电路及其系统
公开(公告)号：US20110043287A1
公开(公告)日：2011-02-24
申请号：US12545084
申请日：2009-08-21
申请人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
发明人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F1/0266 , H03F1/56 , H03F3/195 , H03F3/245 , H03F2200/108 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2200/555
摘要： An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.
摘要翻译：使用相对于功率电平提供更灵敏的自适应偏置电流的自适应偏置电路用于偏置电子电路。自适应偏置电路具有耦合到电源的第一晶体管，耦合到第一晶体管的电压偏置电路和偏置第一晶体管的电源，以及耦合到第一晶体管和电子电路的第一功率耦合模块，用于耦合输入信号功率的一部分到第一晶体管。第二晶体管耦合到第一晶体管和电源以增加自适应偏置电路的电流增益，并且第二电流耦合模块耦合到第二晶体管和电子电路以向电子电路提供自适应偏置电流。

5. 发明授权

US07692493B1 High-efficiency single to differential amplifier 有权
标题翻译：高效单差分放大器
公开(公告)号：US07692493B1
公开(公告)日：2010-04-06
申请号：US12356537
申请日：2009-01-21
申请人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
发明人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F3/191 , H03F1/0261 , H03F3/45085 , H03F3/45098 , H03F2203/45166
摘要： A high-efficiency single-to-differential amplifier has a first transistor acting as a first amplification stage. A second transistor, a third transistor, a first choke, a second choke, and a first capacitor form a second single-to-differential amplification stage. The first amplification stage receives and amplifies an input signal, outputs the amplified signal to the second single-to-differential amplification stage through a coupling module, and concurrently provides DC bias current to the second single-to-differential amplification stage through a tank. The second single-to-differential amplification stage reuses DC current of the first amplification stage, amplifies the output signal of the first amplification stage, and transfers it to a differential output.
摘要翻译：高效率的单对差分放大器具有作为第一放大级的第一晶体管。第二晶体管，第三晶体管，第一扼流圈，第二扼流圈和第一电容器形成第二单差放大级。第一放大级接收并放大输入信号，通过耦合模块将放大的信号输出到第二单差分放大级，并通过一个容器向第二单差放大级提供DC偏置电流。第二单差分放大级重新利用第一放大级的直流电流，放大第一放大级的输出信号，并将其传送到差分输出。

6. 发明授权

US06870387B2 Method and test structures for measuring interconnect coupling capacitance in an IC chip 失效
标题翻译：用于测量IC芯片中互连耦合电容的方法和测试结构
公开(公告)号：US06870387B2
公开(公告)日：2005-03-22
申请号：US10699830
申请日：2003-11-04
申请人： Kai-Ye Huang , Chuan-Jane Chao
发明人： Kai-Ye Huang , Chuan-Jane Chao
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/2853
摘要： Measurement method and test structures for measuring interconnect coupling capacitance in an IC chip are provided. This method employs CBCM technique. In the first step, two test structures are used to measure a target configuration in order to obtain the total capacitance C of a metal line with respect to ground including line-to-line, fringe and area components (C=2Cc+2Cf+Ca). In the second step, two other test structures are used to measure a dummy configuration in order to obtain the area and fringe capacitance Cdummy of the metal line with respect to ground including fringe and area components (Cdummy=2Cf+Ca). After the two steps, the coupling capacitance Cc between the metal line and another line can be determined according to the formula Cc=(C−Cdummy)/2.
摘要翻译：提供了用于测量IC芯片中的互连耦合电容的测量方法和测试结构。该方法采用CBCM技术。在第一步中，使用两个测试结构来测量目标结构，以获得金属线相对于包括线对线，边缘和面积分量的金属线的总电容C（C = 2Cc + 2Cf + Ca ）。在第二步中，为了获得金属线相对于包括边缘和面积分量（Cdummy = 2Cf + Ca）的地面的金属线的面积和边缘电容Cdummy，使用另外两个测试结构来测量虚拟配置。在两步之后，可以根据公式Cc =（C-Cdummy）/ 2来确定金属线与另一条线之间的耦合电容Cc。

7. 发明申请

US20050024077A1 Method and test structures for measuring interconnect coupling capacitance in an IC chip 失效
标题翻译：用于测量IC芯片中互连耦合电容的方法和测试结构
公开(公告)号：US20050024077A1
公开(公告)日：2005-02-03
申请号：US10699830
申请日：2003-11-04
申请人： Kai-Ye Huang , Chuan-Jane Chao
发明人： Kai-Ye Huang , Chuan-Jane Chao
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/2853
摘要： Measurement method and test structures for measuring interconnect coupling capacitance in an IC chip are provided. This method employs CBCM technique. In the first step, two test structures are used to measure a target configuration in order to obtain the total capacitance C of a metal line with respect to ground including line-to-line, fringe and area components(C=2Cc+2Cf+Ca). In the second step, two other test structures are used to measure a dummy configuration in order to obtain the area and fringe capacitance Cdummy of the metal line with respect to ground including fringe and area components (Cdummy=2Cf+Ca). After the two steps, the coupling capacitance Cc between the metal line and another line can be determined according to the formula Cc=(C-Cdummy)/2.
摘要翻译：提供了用于测量IC芯片中的互连耦合电容的测量方法和测试结构。该方法采用CBCM技术。在第一步中，使用两个测试结构来测量目标结构，以获得金属线相对于包括线对线，边缘和面积分量的金属线的总电容C（C = 2Cc + 2Cf + Ca ）。在第二步中，为了获得金属线相对于包括边缘和面积分量（Cdummy = 2Cf + Ca）的地面的面积和边缘电容Cdummy，使用另外两个测试结构来测量虚拟配置。在两步之后，可以根据公式Cc =（C-Cdummy）/ 2来确定金属线与另一条线之间的耦合电容Cc。

8. 发明申请

US20110291226A1 Compound Semiconductor Device and Method for Fabricating the Same 有权
标题翻译：复合半导体器件及其制造方法
公开(公告)号：US20110291226A1
公开(公告)日：2011-12-01
申请号：US12967289
申请日：2010-12-14
申请人： Kuo-Jui Peng , Chuan-Jane Chao , Tsyr-Shyang Liou
发明人： Kuo-Jui Peng , Chuan-Jane Chao , Tsyr-Shyang Liou
IPC分类号： H01L29/66 , H01L21/02
CPC分类号： H01L29/92 , H01L27/0605 , H01L29/20 , H01L29/8605
摘要： A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.
摘要翻译：提供了一种化合物半导体器件，其包括具有第一突出部分和第二突出部分的砷化镓（GaAs）衬底，其中第一突出部分形成在GaAs衬底的第一部分上，并且第二突起形成在第二突起部分上部分GaAs衬底。第一元件设置在第一突出部分上方，第二元件设置在第二突起部分上。

9. 发明授权

US07671704B2 LC resonant circuit 有权
标题翻译： LC谐振电路
公开(公告)号：US07671704B2
公开(公告)日：2010-03-02
申请号：US11819281
申请日：2007-06-26
申请人： Chia-Jen Hsu , Chuan-Jane Chao
发明人： Chia-Jen Hsu , Chuan-Jane Chao
IPC分类号： H03H7/01
CPC分类号： H03H5/00 , H01F17/0006 , H01F27/40
摘要： An LC resonant circuit. The LC resonant circuit comprises an inductor and a conductor. The inductor is an electrode plate of a capacitor. The conductor is over, under, or on both sides of the inductor and used as the other electrode plate of the capacitor.
摘要翻译： LC谐振电路。 LC谐振电路包括一个电感和一个导体。电感器是电容器的电极板。导体在电感器的两侧，下面或两侧，用作电容器的另一个电极板。

10. 发明授权

US06541325B2 Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby 失效
公开(公告)号：US06541325B2
公开(公告)日：2003-04-01
申请号：US10136118
申请日：2002-05-01
申请人： Chih-Mu Huang , Chuan-Jane Chao , Chi-Hung Kao
发明人： Chih-Mu Huang , Chuan-Jane Chao , Chi-Hung Kao
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L27/0635
摘要： The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

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