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1. 发明授权

US06150730A Chip-scale semiconductor package 有权
标题翻译：芯片级半导体封装
公开(公告)号：US06150730A
公开(公告)日：2000-11-21
申请号：US349231
申请日：1999-07-08
申请人： Chih-Ming Chung , Kuo-Pin Yang , Jen-Kuang Fang , Su Tao
发明人： Chih-Ming Chung , Kuo-Pin Yang , Jen-Kuang Fang , Su Tao
IPC分类号： H01L23/495 , H01L23/498 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/4951 , H01L23/49816 , H01L23/49827 , H01L24/50 , H01L2924/14
摘要： A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.
摘要翻译：芯片级半导体封装主要包括半导体芯片，基板和封装体。所述芯片通过粘合剂层附着在所述基板上。所述芯片具有形成在其上的多个接合焊盘。所述粘合剂层具有对应于所述芯片的焊盘的孔，使得焊盘可以暴露在孔内。所述衬底具有分别对应于所述芯片的焊盘和所述芯片的边缘周围区域的部分的多个通孔，用于在将所述衬底的引线焊接到所述芯片的焊盘之后分配密封剂。分配到通孔中的密封剂可以从所述芯片的表面流动到其边缘。所述封装体具有设置在所述基板的通孔内的一部分和设置在所述芯片的边缘周围的另一部分，从而实现封装处理而不必转动整个半导体封装器件。

2. 发明授权

US06692581B2 Solder paste for fabricating bump 有权
标题翻译：用于制造凸块的焊膏
公开(公告)号：US06692581B2
公开(公告)日：2004-02-17
申请号：US10248802
申请日：2003-02-20
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Ching-Fu Horng , Shih-Kuang Chen , Shyh-Ing Wu , Chun-Hung Lin , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Ching-Fu Horng , Shih-Kuang Chen , Shyh-Ing Wu , Chun-Hung Lin , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： B23K35363
CPC分类号： H01L24/10 , B23K35/0244 , B23K35/025 , B23K35/262 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/0103 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K3/3484 , H05K2201/0266 , H05K2203/043 , H01L2924/00
摘要： A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.
摘要翻译：用于制造凸块的焊膏包括焊剂和金属合金粉末。金属合金粉末包含多个低共晶金属合金颗粒，这些金属合金颗粒的尺寸为20-60μm，金属颗粒的平均尺寸为35μm〜45μm。

3. 发明授权

US06664128B2 Bump fabrication process 有权
标题翻译：凸起制造工艺
公开(公告)号：US06664128B2
公开(公告)日：2003-12-16
申请号：US10248716
申请日：2003-02-12
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： H01L2144
CPC分类号： C25F3/02 , C23F1/26 , H01L21/32134 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/1147 , H01L2224/131 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/3473 , H05K2203/054 , H01L2224/13099 , H01L2924/00014
摘要： The present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps in sequence over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant mainly comprises sulfuric acid and de-ionized water. The etchant can etch the nickel-vanadium layer of the UBM layer without damaging the bumps.
摘要翻译：本发明提供一种凸块制造工艺。在衬底上顺序地形成凹凸不平的冶金（UBM）层和凸块之后，用蚀刻剂蚀刻未被凸块覆盖的凸块下金属层。蚀刻剂主要包括硫酸和去离子水。蚀刻剂可以蚀刻UBM层的镍钒层，而不会损坏凸块。

4. 发明授权

US06927964B2 Structure for preventing burnt fuse pad from further electrical connection 有权
标题翻译：用于防止烧坏的保险丝垫进一步电连接的结构
公开(公告)号：US06927964B2
公开(公告)日：2005-08-09
申请号：US10604772
申请日：2003-08-15
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： H01L21/60 , H01L23/31 , H01L23/525 , H02H5/00
CPC分类号： H01L24/12 , H01L23/3171 , H01L23/5258 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05556 , H01L2224/05572 , H01L2224/13099 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/12042 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.
摘要翻译：具有能力的半导体器件可以防止燃烧的熔丝焊盘再次电连接，其中半导体器件包括凸块焊盘和晶片上的熔丝焊盘。保险丝座包括具有用于电隔离的间隙的燃烧的保险丝座。该半导体器件包括介于绝缘层上的绝缘层，该绝缘层基本上设置在烧结的熔丝焊盘的上方并填充间隙，以及设置在凸点焊盘上的凸块结构。上述半导体器件还可以包括钝化层，其暴露凸块焊盘和烧焦的熔丝焊盘的一部分。其中，电介质层在钝化层上方，覆盖烧结的熔丝垫的暴露部分并填充间隙。

5. 发明授权

US06846719B2 Process for fabricating wafer bumps 有权
标题翻译：制造晶圆凸块的工艺
公开(公告)号：US06846719B2
公开(公告)日：2005-01-25
申请号：US10248804
申请日：2003-02-20
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： H01L21/60 , H01L21/76
CPC分类号： H01L24/05 , H01L24/02 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05027 , H01L2224/05572 , H01L2224/056 , H01L2224/1147 , H01L2224/13099 , H01L2924/0002 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2224/05552
摘要： A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.
摘要翻译：在本发明中提供了晶片凸块制造工艺。提供具有多个接合焊盘的晶片和暴露焊接焊盘的钝化层。每个焊盘的表面具有凸块下的冶金层。形成具有多个开口的图案化光致抗蚀剂层，这些开口暴露凸块下金属层。之后进行固化工艺以固化图案化的光致抗蚀剂层。进行焊膏填充处理以将焊膏填充到开口中。进行回流处理以从开口中的焊膏形成凸起。去除图案化的光致抗蚀剂层。

6. 发明授权

US06617237B1 Lead-free bump fabrication process 有权
标题翻译：无铅凸块制造工艺
公开(公告)号：US06617237B1
公开(公告)日：2003-09-09
申请号：US10248882
申请日：2003-02-27
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/11332 , H01L2224/11334 , H01L2224/1147 , H01L2224/13099 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： A lead-free solder bump fabrication process for producing a plurality of lead-free solder bumps over a wafer is provided. The lead-free solder bump fabrication process includes forming a lead-free pre-formed solder bump over each bonding pad on the wafer and then forming a patterned solder mask layer over the active surface of the wafer. The openings in the solder mask layer expose the respective lead-free pre-formed solder bumps on the wafer. Thereafter, lead-free solder material is deposited into the opening. The material composition of the lead-free solder material differs from the material composition of the lead-free pre-formed solder bump. A reflow process is conducted so that the lead-free pre-formed solder bump fuses with the lead-free solder material to form a lead-free solder bump. Finally, the solder mask layer is removed.
摘要翻译：提供了一种用于在晶片上产生多个无铅焊料凸块的无铅焊料凸块制造工艺。无铅焊料凸块制造工艺包括在晶片上的每个接合焊盘上形成无铅预成形焊料凸块，然后在晶片的有效表面上形成图案化的焊接掩模层。焊接掩模层中的开口露出晶片上的相应的无铅预制焊料凸点。此后，将无铅焊料材料沉积到开口中。无铅焊料的材料组成不同于无铅预成形焊料凸块的材料组成。进行回流处理，使得无铅预成形焊料凸块与无铅焊料材料熔合以形成无铅焊料凸块。最后，去除焊接掩模层。

7. 发明授权

US06342443B1 Method and structure for forming flip chip with collapse-controlled solder bumps on a substrate 有权
标题翻译：用于在基板上形成具有塌陷控制的焊料凸块的倒装芯片的方法和结构
公开(公告)号：US06342443B1
公开(公告)日：2002-01-29
申请号：US09346735
申请日：1999-07-02
申请人： Su Tao , Wei-Chung Wang , Jen-Kuang Fang
发明人： Su Tao , Wei-Chung Wang , Jen-Kuang Fang
IPC分类号： H01L2144
CPC分类号： H01L24/14 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/1131 , H01L2224/1184 , H01L2224/11849 , H01L2224/13111 , H01L2224/1357 , H01L2224/136 , H01L2224/81211 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H05K3/3436 , H05K3/3463 , H05K2201/0379 , H05K2201/10992 , H05K2203/013 , Y02P70/613 , H01L2224/13099 , H01L2924/00 , H01L2224/0401
摘要： A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.
摘要翻译：首先提供具有C4焊料凸块的模具和聚合物基板的封装工艺。然后将熔化的第二焊料喷射到形成第二焊料凸块的每个C4焊料凸块上。在回流和调平焊料凸块之后，将模具翻转并与基板组合。然后热处理随着管芯和衬底的组合进行，在聚合物衬底上形成具有塌陷控制的焊料凸块的倒装芯片封装。

8. 发明授权

US06877653B2 Method of modifying tin to lead ratio in tin-lead bump 有权
标题翻译：锡铅凸点中锡与铅比的修改方法
公开(公告)号：US06877653B2
公开(公告)日：2005-04-12
申请号：US10248411
申请日：2003-01-17
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： B23K35/02 , B23K35/26 , H05K3/34 , B23K31/02 , B23K31/00 , B23K35/24
CPC分类号： H05K3/3484 , B23K35/0244 , B23K35/025 , B23K35/262 , B23K35/268 , H05K3/3463 , H05K2201/0379 , H05K2203/043 , H05K2203/0568
摘要： A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.
摘要翻译：改变锡铅凸块的锡引导比的方法在衬底上形成图案化的焊料掩模，该衬底包括形成在其上的第一锡铅凸块，所述图案化焊料掩模具有暴露锡铅凸块的开口。包括锡和铅的焊料材料填充在第一锡铅凸块上的焊料掩模的开口中。焊锡材料具有与第一锡铅凸块不同的锡与引线比。焊料材料被回流以与形成第二锡铅凸块的第一锡铅凸块熔合。因此，第二锡铅凸块的锡与引线比不同于第一锡铅凸块的锡引导比。

9. 发明授权

US06756256B2 Method for preventing burnt fuse pad from further electrical connection 有权
标题翻译：防止燃烧保险丝垫进一步电连接的方法
公开(公告)号：US06756256B2
公开(公告)日：2004-06-29
申请号：US10248803
申请日：2003-02-20
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： H01L2182
CPC分类号： H01L24/12 , H01L23/3171 , H01L23/5258 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05556 , H01L2224/05572 , H01L2224/13099 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/12042 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.
摘要翻译：一种在晶片上形成凸起之前防止燃烧保险丝垫进一步电连接的方法。在覆盖凸块焊盘和晶片的熔断体的晶片的有源表面上形成电介质层，其中熔断器的中心区域被烧结以形成间隙，该间隙允许电介质层的材料填满间隙。之后，除去介电层的一部分，并且覆盖覆盖焊盘的电介质层的一部分覆盖熔丝焊盘的介电层的一部分被去除。然后，在晶片的凸块焊盘上形成球下冶金层，使得球下冶金层的材料不会同时覆盖熔丝焊盘的两侧或者填充到间隙中。结果，电隔离仍然存在。

10. 发明授权

US6153939A Flip-chip semiconductor device with enhanced reliability and manufacturing efficiency, and the method for under filling the same 有权
标题翻译：具有提高的可靠性和制造效率的倒装芯片半导体器件，以及用于填充其的方法
公开(公告)号：US6153939A
公开(公告)日：2000-11-28
申请号：US317354
申请日：1999-05-24
申请人： Wei-Chung Wang , Hsueh-Te Wang , Jen-Kuang Fang , Su Tao
发明人： Wei-Chung Wang , Hsueh-Te Wang , Jen-Kuang Fang , Su Tao
IPC分类号： H01L21/56 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/563 , H01L24/28 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/15151 , H01L2924/351
摘要： A flip-chip semiconductor device and a method for under filling the flip-chip semiconductor device are disclosed. The flip-chip semiconductor device is provided with a substrate and a die having a plurality of solder bumps for connecting to the substrate. Encapsulation material is under filled between the die and the substrate. The substrate has a non-mask area defied in a center portion thereof while the remaining surface area is covered by a solder mask. The non-mask area defines a hole in the center thereof so that the encapsulation material can be dispensed along all sides of the die to flow toward the non-mask area and stop when reaching the non-mask area whereby the encapsulation material does not block the hole and air between said die and the substrate is limited in a void formed around the hole and communicated with the atmosphere via the hole.
摘要翻译：公开了一种倒装芯片半导体器件和用于填充倒装芯片半导体器件的方法。倒装芯片半导体器件设置有具有用于连接到衬底的多个焊料凸块的衬底和管芯。封装材料在模具和基板之间被填充。基板在其中心部分具有不掩蔽的非掩模区域，而剩余表面积被焊接掩模覆盖。非掩模区域在其中心限定一个孔，使得封装材料可以沿芯片的所有侧面分配以流向非掩模区域，并在达到非掩模区域时停止，从而封装材料不会阻塞所述模具和基板之间的孔和空气被限制在形成在孔周围并且经由孔与大气连通的空隙中。

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