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    • 1. 发明申请
    • SHIFT REGISTER
    • 移位寄存器
    • US20110044423A1
    • 2011-02-24
    • US12615247
    • 2009-11-09
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • G11C19/00
    • G11C19/28G09G3/32G09G2310/0286
    • A shift register includes a plurality of electrically connected shift units. Each shift unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit outputs a first signal to an output node according to the first signal and a voltage of a driving node. The pull-up driving drives the pull-up circuit according to an output voltage of the previous shift unit. The pull-down driving circuit outputs a low level voltage to the driving node and the output node according to the first signal and a second signal. The pull-down circuit resets the pull-up driving circuit according to the voltage of the output node and outputs the low level voltage to the output node and the driving node according to a third signal and a fourth signal.
    • 移位寄存器包括多个电连接的移位单元。 每个移位单元包括上拉电路,上拉驱动电路,下拉电路和下拉驱动电路。 上拉电路根据第一信号和驱动节点的电压向输出节点输出第一信号。 上拉驱动根据前一个移位单元的输出电压驱动上拉电路。 下拉驱动电路根据第一信号和第二信号向驱动节点和输出节点输出低电平电压。 下拉电路根据输出节点的电压来复位上拉驱动电路,并根据第三信号和第四信号将低电平电压输出到输出节点和驱动节点。
    • 2. 发明授权
    • Shift register
    • 移位寄存器
    • US08081731B2
    • 2011-12-20
    • US12615247
    • 2009-11-09
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • G11C19/00
    • G11C19/28G09G3/32G09G2310/0286
    • A shift register includes a plurality of electrically connected shift units. Each shift unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit outputs a first signal to an output node according to the first signal and a voltage of a driving node. The pull-up driving drives the pull-up circuit according to an output voltage of the previous shift unit. The pull-down driving circuit outputs a low level voltage to the driving node and the output node according to the first signal and a second signal. The pull-down circuit resets the pull-up driving circuit according to the voltage of the output node and outputs the low level voltage to the output node and the driving node according to a third signal and a fourth signal.
    • 移位寄存器包括多个电连接的移位单元。 每个移位单元包括上拉电路,上拉驱动电路,下拉电路和下拉驱动电路。 上拉电路根据第一信号和驱动节点的电压向输出节点输出第一信号。 上拉驱动根据前一个移位单元的输出电压驱动上拉电路。 下拉驱动电路根据第一信号和第二信号向驱动节点和输出节点输出低电平电压。 下拉电路根据输出节点的电压来复位上拉驱动电路,并根据第三信号和第四信号将低电平电压输出到输出节点和驱动节点。
    • 3. 发明授权
    • Shift register circuit having bi-directional transmission mechanism
    • 移位寄存器电路具有双向传输机制
    • US07929658B2
    • 2011-04-19
    • US12605359
    • 2009-10-25
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • G11C19/00
    • G11C19/28
    • A shift register includes a plurality of shift register stages for providing gate signals. Each shift register stage has a pull-up unit, a carry unit, a carry control unit, an input unit and a pull-down unit. The pull-up unit is employed to pull up a gate signal according to a driving control voltage and a first clock. The carry unit generates a preliminary start pulse signal based on the driving control voltage and the first clock. The carry control unit outputs the preliminary start pulse signal to become a forward or backward start pulse signal according to first and second bias voltages. The input unit is utilized for inputting a start pulse signal generated by a preceding or succeeding shift register stage to become the driving control voltage. The pull-down unit pulls down the gate signal, the preliminary start pulse signal and the driving control voltage according to multiple clocks.
    • 移位寄存器包括用于提供门信号的多个移位寄存器级。 每个移位寄存器级具有上拉单元,进位单元,进位控制单元,输入单元和下拉单元。 上拉单元用于根据驱动控制电压和第一时钟上拉栅极信号。 进位单元基于驱动控制电压和第一时钟产生初步启动脉冲信号。 进位控制单元根据第一和第二偏置电压输出初步起始脉冲信号以成为正向或反向启动脉冲信号。 输入单元用于输入由前一个或后一个移位寄存器级产生的起始脉冲信号,以成为驱动控制电压。 下拉单元根据多个时钟下拉门信号,初始启动脉冲信号和驱动控制电压。
    • 4. 发明申请
    • SHIFT REGISTER CIRCUIT HAVING BI-DIRECTIONAL TRANSMISSION MECHANISM
    • 具有双向传输机制的移位寄存器电路
    • US20110013740A1
    • 2011-01-20
    • US12605359
    • 2009-10-25
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • Chih-Lung LinChun-Da TuYung-Chih Chen
    • G11C19/00
    • G11C19/28
    • A shift register includes a plurality of shift register stages for providing gate signals. Each shift register stage has a pull-up unit, a carry unit, a carry control unit, an input unit and a pull-down unit. The pull-up unit is employed to pull up a gate signal according to a driving control voltage and a first clock. The carry unit generates a preliminary start pulse signal based on the driving control voltage and the first clock. The carry control unit outputs the preliminary start pulse signal to become a forward or backward start pulse signal according to first and second bias voltages. The input unit is utilized for inputting a start pulse signal generated by a preceding or succeeding shift register stage to become the driving control voltage. The pull-down unit pulls down the gate signal, the preliminary start pulse signal and the driving control voltage according to multiple clocks.
    • 移位寄存器包括用于提供门信号的多个移位寄存器级。 每个移位寄存器级具有上拉单元,进位单元,进位控制单元,输入单元和下拉单元。 上拉单元用于根据驱动控制电压和第一时钟上拉栅极信号。 进位单元基于驱动控制电压和第一时钟产生初步启动脉冲信号。 进位控制单元根据第一和第二偏置电压输出初步起始脉冲信号以成为正向或反向启动脉冲信号。 输入单元用于输入由前一个或后一个移位寄存器级产生的起始脉冲信号,以成为驱动控制电压。 下拉单元根据多个时钟下拉门信号,初始启动脉冲信号和驱动控制电压。
    • 5. 发明授权
    • ESD protection circuit and display apparatus using the same
    • ESD保护电路及使用其的显示装置
    • US08350841B2
    • 2013-01-08
    • US13016302
    • 2011-01-28
    • Chia-Sheng LiYung-Chih ChenChih-Lung Lin
    • Chia-Sheng LiYung-Chih ChenChih-Lung Lin
    • G06F3/038G09G5/00H02H3/20H02H9/04H02H9/00H02H3/22
    • G09G3/20G09G3/3648G09G2330/04
    • An ESD protection circuit comprises three transistors and two voltage dividers. The two source/drain terminals of a first transistor are electrically coupled to a first power line and a second power line respectively. The two source/drain terminals of a second transistor are electrically coupled to the first power line and a gate terminal of the first transistor respectively. The two source/drain terminals of a third transistor are electrically coupled to the gate terminal of the first transistor and the second power line respectively. A first voltage divider supplies a first voltage to a gate terminal of the second transistor according to a potential difference between the first power line and the second power line. A second voltage divider supplies a second voltage to a gate terminal of the third transistor according to the potential difference between the first power line and the second power line.
    • ESD保护电路包括三个晶体管和两个分压器。 第一晶体管的两个源极/漏极端子分别电耦合到第一电力线和第二电力线。 第二晶体管的两个源极/漏极端子分别电耦合到第一电源线和第一晶体管的栅极端子。 第三晶体管的两个源极/漏极端子分别电耦合到第一晶体管和第二电源线的栅极端子。 第一分压器根据第一电力线和第二电力线之间的电位差向第二晶体管的栅极端子提供第一电压。 第二分压器根据第一电力线和第二电力线之间的电位差向第三晶体管的栅极端子提供第二电压。
    • 7. 发明申请
    • ESD PROTECTION CIRCUIT AND DISPLAY APPARATUS USING THE SAME
    • 防静电保护电路及显示装置
    • US20110285690A1
    • 2011-11-24
    • US13016302
    • 2011-01-28
    • Chia-Sheng LIYung-Chih ChenChih-Lung Lin
    • Chia-Sheng LIYung-Chih ChenChih-Lung Lin
    • G09G5/00H02H9/04
    • G09G3/20G09G3/3648G09G2330/04
    • An ESD protection circuit comprises three transistors and two voltage dividers. The two source/drain terminals of a first transistor are electrically coupled to a first power line and a second power line respectively. The two source/drain terminals of a second transistor are electrically coupled to the first power line and a gate terminal of the first transistor respectively. The two source/drain terminals of a third transistor are electrically coupled to the gate terminal of the first transistor and the second power line respectively. A first voltage divider supplies a first voltage to a gate terminal of the second transistor according to a potential difference between the first power line and the second power line. A second voltage divider supplies a second voltage to a gate terminal of the third transistor according to the potential difference between the first power line and the second power line.
    • 一个ESD保护电路包括三个晶体管和两个分压器。 第一晶体管的两个源极/漏极端子分别电耦合到第一电力线和第二电力线。 第二晶体管的两个源极/漏极端子分别电耦合到第一电源线和第一晶体管的栅极端子。 第三晶体管的两个源极/漏极端子分别电耦合到第一晶体管和第二电源线的栅极端子。 第一分压器根据第一电力线和第二电力线之间的电位差向第二晶体管的栅极端子提供第一电压。 第二分压器根据第一电力线和第二电力线之间的电位差向第三晶体管的栅极端子提供第二电压。