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1. 发明授权

US06787484B2 Method of reducing visible light induced arcing in a semiconductor wafer manufacturing process 失效
标题翻译：在半导体晶片制造工艺中减少可见光诱发电弧的方法
公开(公告)号：US06787484B2
公开(公告)日：2004-09-07
申请号：US10322412
申请日：2002-12-17
申请人： Chih-Hsiang Yao , Yun-Cheng Lu
发明人： Chih-Hsiang Yao , Yun-Cheng Lu
IPC分类号： H01L21425
CPC分类号： H01L21/0274 , H01L21/31116 , H01L21/76829 , H01L21/76832
摘要： A method for reducing electrical discharges within semiconductor wafers including providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process water; and, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.
摘要翻译：一种用于减少半导体晶片内的放电的方法，包括提供包括至少一个包括金属互连的介电绝缘层的半导体工艺晶片; 将半导体工艺晶片暴露于半导体工艺，由此电荷不平衡累积在半导体工艺水的部分内; 并且在进行后续处理以在半导体处理晶片内产生的光电流的水平之前，将半导体处理晶片限制在包括波长大于预定下限的可见光的一段时间内。

2. 发明授权

US08669661B2 Metal line and via formation using hard masks 有权
标题翻译：金属线和通孔形成使用硬掩模
公开(公告)号：US08669661B2
公开(公告)日：2014-03-11
申请号：US13370919
申请日：2012-02-10
申请人： Chih-Hsiang Yao , Ying-Wen Huang
发明人： Chih-Hsiang Yao , Ying-Wen Huang
IPC分类号： H01L23/12 , H01L21/4763
CPC分类号： H01L23/522 , H01L21/02063 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76816 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are aligned to a straight line. A dummy metal line interconnects the two dummy metal patterns. A width of the dummy metal line is smaller than lengths and widths of the two dummy metal patterns, wherein the width is measure in a direction perpendicular to the straight line. Bottoms of the two dummy metal patterns and the dummy metal line are substantially level with a bottom surface of the metal line.
摘要翻译：一种器件包括电介质层，电介质层中的金属线以及下面并连接到金属线的通孔。两个虚拟金属图案与金属线相邻，并且与直线对准。虚拟金属线将两个虚拟金属图案互连。虚拟金属线的宽度小于两个虚拟金属图案的长度和宽度，其中宽度在垂直于直线的方向上测量。两个虚拟金属图案和虚拟金属线的底部基本上与金属线的底面平齐。

3. 发明授权

US08450200B2 Method for stacked contact with low aspect ratio 有权
标题翻译：低纵横比堆叠接触的方法
公开(公告)号：US08450200B2
公开(公告)日：2013-05-28
申请号：US12973707
申请日：2010-12-20
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chih-Hsiang Yao , Wen-Kai Wan , Jye-Yen Cheng
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chih-Hsiang Yao , Wen-Kai Wan , Jye-Yen Cheng
IPC分类号： H01L21/44
CPC分类号： H01L23/485 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.
摘要翻译：集成电路结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成金属化层; 在所述半导体衬底和所述金属化层之间形成第一电介质层; 在所述半导体衬底和所述金属化层之间形成第二电介质层，其中所述第二电介质层在所述第一电介质层的上方; 以及形成具有基本上在所述第二介电层中的上部的接触塞和基本在所述第一介电层中的下部。接触插塞电连接到金属化层中的金属线。接触塞在上部和下部之间的界面处不连续。

4. 发明申请

US20080003820A1 Bonding pad structure and method for making the same 有权
标题翻译：粘接垫结构及其制作方法
公开(公告)号：US20080003820A1
公开(公告)日：2008-01-03
申请号：US11477940
申请日：2006-06-30
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Chin-Chiu Hsia
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Chin-Chiu Hsia
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/48463 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2224/05552 , H01L2224/45099
摘要： A semiconductor device, comprising: a substrate with a dielectric layer thereon; a stack of interconnection structures in the dielectric layer, each interconnection structure comprising a conductive layer and a layer of plugs connecting the conductive layer, at least a layer of plugs comprising a crack stopper; and a bonding pad structure with a predetermined bump area thereon, overlying the stack of interconnection structures; wherein the crack stopper is formed along an edge of a projection area corresponding to the predetermined bump area.
摘要翻译：一种半导体器件，包括：其上具有介电层的衬底; 每个互连结构包括导电层和连接导电层的插塞层，至少一个包含裂纹塞的塞子层; 以及在其上覆盖有互连结构的堆叠的具有预定凸块面积的焊盘结构; 其中所述裂纹阻挡件沿着与所述预定凸起区域对应的投影区域的边缘形成。

5. 发明申请

US20070269907A1 Novel conductor layout technique to reduce stress-induced void formations 有权
标题翻译：新型导体布置技术，以减少应力引起的空隙形成
公开(公告)号：US20070269907A1
公开(公告)日：2007-11-22
申请号：US11438127
申请日：2006-05-22
申请人： Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
发明人： Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/768 , H01L23/528 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.
摘要翻译：通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。退火过程导致在导线和绝缘体材料内形成残余应力。在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

6. 发明申请

US20070096092A1 Semiconductor device fault detection system and method 有权
标题翻译：半导体器件故障检测系统及方法
公开(公告)号：US20070096092A1
公开(公告)日：2007-05-03
申请号：US11264911
申请日：2005-11-02
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Kuan-Shou Chi , Wen-Kai Wan
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Kuan-Shou Chi , Wen-Kai Wan
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.
摘要翻译：公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。多个故障检测链从邻近的外边界延伸到密封环内。多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征，以及通过第三通孔耦合到第二金属特征的衬底接触。

7. 发明授权

US07081679B2 Structure and method for reinforcing a bond pad on a chip 有权
标题翻译：用于加强芯片上的接合焊盘的结构和方法
公开(公告)号：US07081679B2
公开(公告)日：2006-07-25
申请号：US10731983
申请日：2003-12-10
申请人： Tai-Chun Huang , Chih-Hsiang Yao
发明人： Tai-Chun Huang , Chih-Hsiang Yao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05624 , H01L2224/05647 , H01L2224/131 , H01L2224/48463 , H01L2224/85207 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A structure for reinforcing or anchoring a bond pad on a chip. The structure includes a bonding pad provided in a dielectric layer, at least one conductive layer provided beneath and in electrical contact with the bonding pad, and at least one parallel-interconnect anchor structure provided in contact with the bonding pad and the conductive layer. The anchor structure or structures prevent the bonding pad from exerting excessive force against the dielectric layer and cracking the dielectric layer when the chip is subjected to physical testing. The bonding pad may have truncated or curved corners, for example.
摘要翻译：用于加强或固定芯片上的焊盘的结构。该结构包括设置在电介质层中的接合焊盘，设置在接合焊盘下方并与接合焊盘电接触的至少一个导电层以及与接合焊盘和导电层接触地设置的至少一个平行互连锚固结构。锚定结构或结构防止接合焊盘在芯片进行物理测试时对电介质层施加过大的力并破坏电介质层。例如，接合焊盘可以具有截头或弯曲的拐角。

8. 发明授权

US06787803B1 Test patterns for measurement of low-k dielectric cracking thresholds 失效
标题翻译：用于测量低k电介质裂纹阈值的测试模式
公开(公告)号：US06787803B1
公开(公告)日：2004-09-07
申请号：US10602970
申请日：2003-06-24
申请人： Chih-Hsiang Yao , Tai-Chun Huang
发明人： Chih-Hsiang Yao , Tai-Chun Huang
IPC分类号： H01L2166
CPC分类号： H01L22/34
摘要： The present invention provides two or more test structures/substructures (100) that are used in a test pattern (500, 600, 700, 800) to determine a cracking threshold for a dielectric material (104) on a substrate. Each test structure/substructure (100) includes two metal structures (102) separated by the dielectric material (104) having a width (G) which is different for each test structure/substructure (100). The cracking threshold will be approximately equal to the largest width (G) of dielectric material (104) that is cracked after processing. The present invention also provides a method for determining the cracking threshold for the dielectric material (104). Two or more test structures (100) are formed on the substrate (402) followed by a determination of whether the dielectric material (104) between the two metal structures (102) for each test structure (100) has cracked during processing (404).
摘要翻译：本发明提供了两个或更多个在测试图案（500,600,700,800）中使用以测定衬底上的电介质材料（104）的裂纹阈值的测试结构/子结构（100）。每个测试结构/子结构（100）包括由介电材料（104）分开的两个金属结构（102），其宽度（G）对于每个测试结构/子结构（100）是不同的。裂纹阈值将近似等于加工后破裂的电介质材料（104）的最大宽度（G）。本发明还提供了一种用于确定介电材料（104）的裂纹阈值的方法。在衬底（402）上形成两个或更多个测试结构（100），随后确定用于每个测试结构（100）的两个金属结构（102）之间的介电材料（104）是否在加工期间已经破裂（404）。

9. 发明授权

US07791070B2 Semiconductor device fault detection system and method 有权
标题翻译：半导体器件故障检测系统及方法
公开(公告)号：US07791070B2
公开(公告)日：2010-09-07
申请号：US11264911
申请日：2005-11-02
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Kuan-Shou Chi , Wen-Kai Wan
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Kuan-Shou Chi , Wen-Kai Wan
IPC分类号： G01R31/26
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.
摘要翻译：公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。多个故障检测链从邻近的外边界延伸到密封环内。多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征，以及通过第三通孔耦合到第二金属特征的衬底接触。

10. 发明申请

US20080191352A1 Stacked contact with low aspect ratio 有权
标题翻译：堆叠接触低纵横比
公开(公告)号：US20080191352A1
公开(公告)日：2008-08-14
申请号：US11706553
申请日：2007-02-13
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chih-Hsiang Yao , Wen-Kai Wan , Jye-Yen Cheng
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chih-Hsiang Yao , Wen-Kai Wan , Jye-Yen Cheng
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。接触插塞电连接到金属化层中的金属线。接触塞在上部和下部之间的界面处是不连续的。

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