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1. 发明申请

US20130334650A1 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US20130334650A1
公开(公告)日：2013-12-19
申请号：US13517573
申请日：2012-06-13
申请人： Chih-Chien Liu , Chia-Lung Chang , Jei-Ming Chen , Jui-Min Lee , Yuh-Min Lin
发明人： Chih-Chien Liu , Chia-Lung Chang , Jei-Ming Chen , Jui-Min Lee , Yuh-Min Lin
IPC分类号： H01L29/06 , H01L21/302
CPC分类号： H01L21/76224 , H01L29/0649
摘要： A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
摘要翻译：半导体结构位于衬底的凹部中。半导体结构包括衬垫，富硅层和填充材料。衬垫位于凹槽的表面上。富硅层位于衬套上。填充材料位于富硅层上并填充凹槽。此外，还提供了形成所述半导体结构的半导体工艺。

2. 发明授权

US08772904B2 Semiconductor structure and process thereof 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US08772904B2
公开(公告)日：2014-07-08
申请号：US13517573
申请日：2012-06-13
申请人： Chih-Chien Liu , Chia-Lung Chang , Jei-Ming Chen , Jui-Min Lee , Yuh-Min Lin
发明人： Chih-Chien Liu , Chia-Lung Chang , Jei-Ming Chen , Jui-Min Lee , Yuh-Min Lin
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76224 , H01L29/0649
摘要： A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
摘要翻译：半导体结构位于衬底的凹部中。半导体结构包括衬垫，富硅层和填充材料。衬垫位于凹槽的表面上。富硅层位于衬套上。填充材料位于富硅层上并填充凹槽。此外，还提供了形成所述半导体结构的半导体工艺。

3. 发明申请

US20140042501A1 MOS TRANSISTOR AND PROCESS THEREOF 审中-公开
标题翻译： MOS晶体管及其工艺
公开(公告)号：US20140042501A1
公开(公告)日：2014-02-13
申请号：US13571369
申请日：2012-08-10
申请人： Jei-Ming Chen , Chih-Chien Liu , Yu-Shu Lin , Tzu-Chin Wu
发明人： Jei-Ming Chen , Chih-Chien Liu , Yu-Shu Lin , Tzu-Chin Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.
摘要翻译： MOS晶体管包括栅极结构和间隔物。栅极结构位于衬底上。间隔件位于栅极结构旁边的基板上，并且间隔件包括L形内部间隔件和外部间隔件，其中外部间隔件位于L形内部间隔件上，并且L形的两个端部内间隔件从外间隔件突出。此外，本发明还提供一种用于形成MOS晶体管的MOS晶体管工艺。

4. 发明授权

US07439154B2 Method of fabricating interconnect structure 有权
标题翻译：制造互连结构的方法
公开(公告)号：US07439154B2
公开(公告)日：2008-10-21
申请号：US11565632
申请日：2006-12-01
申请人： Feng-Yu Hsu , Chih-Chien Liu , Jim-Jey Huang , Jei-Ming Chen
发明人： Feng-Yu Hsu , Chih-Chien Liu , Jim-Jey Huang , Jei-Ming Chen
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect with the conductive part, and then a first UV-absorption layer is formed on the first porous low-k layer and the damascene structure. A second porous low-k layer is formed on the first UV-absorption layer, and a second UV-curing step is conducted.
摘要翻译：描述了制造互连结构的方法。提供其上具有导电部分的基板，在基板上形成第一多孔低k层，然后进行第一UV固化步骤。在第一多孔低k层中形成镶嵌结构以与导电部分电连接，然后在第一多孔低k层和镶嵌结构上形成第一紫外线吸收层。在第一UV吸收层上形成第二多孔低k层，进行第二UV固化步骤。

5. 发明申请

US20060281299A1 METHOD OF FABRICATING SILICON CARBIDE-CAPPED COPPER DAMASCENE INTERCONNECT 审中-公开
标题翻译：硅碳化铜复合物互连的制备方法
公开(公告)号：US20060281299A1
公开(公告)日：2006-12-14
申请号：US11462045
申请日：2006-08-03
申请人： Jei-Ming Chen , Chin-Hsiang Lin , Chih-Chien Liu , Kuo-Chih Lai
发明人： Jei-Ming Chen , Chin-Hsiang Lin , Chih-Chien Liu , Kuo-Chih Lai
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76849 , C23C16/0245 , C23C16/325 , H01L21/3148 , H01L21/76834 , H01L21/76867 , H01L21/76883 , H01L21/76889 , H01L23/48
摘要： A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of the copper or copper alloy then reacts with trimethylsilane or tertramethylsilane under plasma enhanced chemical vapor deposition (PECVD) conditions. Subsequently, by PECVD, a silicon carbide layer is in-situ deposited on the copper or copper alloy.
摘要翻译：准备覆盖衬底的电介质层。镶嵌开口蚀刻到电介质层中。镶嵌开口填充有铜或铜合金。铜或铜合金的表面用含氢等离子体如H 2 N 3或NH 3 3等离子体处理。然后在等离子体增强化学气相沉积（PECVD）条件下，铜或铜合金的处理表面与三甲基硅烷或三甲基硅烷反应。随后，通过PECVD，将碳化硅层原位沉积在铜或铜合金上。

6. 发明申请

US20060199367A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060199367A1
公开(公告)日：2006-09-07
申请号：US11164824
申请日：2005-12-07
申请人： Jim-Jey Huang , Chih-Chien Liu , Feng-Yu Hsu , Jei-Ming Chen , Kuo-Chih Lai
发明人： Jim-Jey Huang , Chih-Chien Liu , Feng-Yu Hsu , Jei-Ming Chen , Kuo-Chih Lai
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of interconnect is provided. A dielectric layer is provided. A metal layer is formed in the dielectric layer. A fluorine-containing barrier layer is formed on the dielectric layer and covers the metal layer. The fluorine-containing barrier layer is formed by using chemical deposition method and introducing fluorine to the film in-situ.
摘要翻译：提供了互连的制造方法。提供介电层。在电介质层中形成金属层。在电介质层上形成含氟阻挡层，覆盖金属层。通过使用化学沉积方法形成含氟阻挡层，并将氟引入到膜中。

7. 发明授权

US06873057B2 Damascene interconnect with bi-layer capping film 有权
标题翻译：大马士革与双层封盖膜相互连接
公开(公告)号：US06873057B2
公开(公告)日：2005-03-29
申请号：US10248750
申请日：2003-02-14
申请人： Jei-Ming Chen , Yi-Fang Chiang , Chih-Chien Liu
发明人： Jei-Ming Chen , Yi-Fang Chiang , Chih-Chien Liu
IPC分类号： H01L21/311 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76883 , H01L21/76832 , H01L21/76834 , H01L21/76835
摘要： A damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300° C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.
摘要翻译：提供具有双层封盖膜的镶嵌互连结构。镶嵌互连结构包括设置在半导体层上的半导体层和介电层。电介质层具有主表面和设置在主表面上的至少一个镶嵌凹部。铜丝嵌入镶嵌的凹槽中。铜线具有化学机械抛光的上表面，其与电介质层的主表面基本上共面。在抛光铜线的上表面之后，在低于300℃的温度下，在导电等离子体环境中对上表面进行预处理和还原。然后在铜线的上表面上设置双层封盖膜。双层封盖膜由较低的HDPCVD氮化硅层和上掺杂碳化硅层组成。

8. 发明授权

US07514347B2 Interconnect structure and fabricating method thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US07514347B2
公开(公告)日：2009-04-07
申请号：US11307161
申请日：2006-01-26
申请人： Feng-Yu Hsu , Chih-Chien Liu , Chun-Chieh Huang , Jei-Ming Chen , Shu-Jen Sung
发明人： Feng-Yu Hsu , Chih-Chien Liu , Chun-Chieh Huang , Jei-Ming Chen , Shu-Jen Sung
IPC分类号： H01L21/44
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
摘要翻译：描述了布置在其上具有导电部分的基板上并且在基板上包括第一多孔低k层的基板上的互连结构，与导电部分电连接的第一多孔低k层中的镶嵌结构，第二多孔低 -k层，以及至少在第一和第二多孔低k层之间的UV切割层，其中UV切割层是UV反射层或UV反射层，吸收层。

9. 发明申请

US20070085210A1 INTERCONNECT STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：互连结构及其制作方法
公开(公告)号：US20070085210A1
公开(公告)日：2007-04-19
申请号：US11307161
申请日：2006-01-26
申请人： Feng-Yu Hsu , Chih-Chien Liu , Chun-Chieh Huang , Jei-Ming Chen , Shu-Jen Sung
发明人： Feng-Yu Hsu , Chih-Chien Liu , Chun-Chieh Huang , Jei-Ming Chen , Shu-Jen Sung
IPC分类号： H01L23/52
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
摘要翻译：描述了布置在其上具有导电部分的基板上并且在基板上包括第一多孔低k层的基板上的互连结构，与导电部分电连接的第一多孔低k层中的镶嵌结构，第二多孔低 -k层，以及至少在第一和第二多孔低k层之间的UV切割层，其中UV切割层是UV反射层或UV反射层，吸收层。

10. 发明申请

US20070085208A1 INTERCONNECT STRUCTURE 审中-公开
标题翻译：互连结构
公开(公告)号：US20070085208A1
公开(公告)日：2007-04-19
申请号：US11163285
申请日：2005-10-13
申请人： Feng-Yu Hsu , Chih-Chien Liu , Jim-Jey Huang , Jei-Ming Chen
发明人： Feng-Yu Hsu , Chih-Chien Liu , Jim-Jey Huang , Jei-Ming Chen
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV-absorption layer at least between the first and the second porous low-k layers.
摘要翻译：描述了布置在其上具有导电部分的基板上并且在基板上包括第一多孔低k层的基板上的互连结构，与导电部分电连接的第一多孔低k层中的镶嵌结构，第二多孔低 -k层在第一多孔低k层和镶嵌结构之上，以及至少在第一和第二多孔低k层之间的UV吸收层。

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