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    • 2. 发明申请
    • Systems and Methods for Lithography Masks
    • 光刻面具的系统和方法
    • US20130323625A1
    • 2013-12-05
    • US13486015
    • 2012-06-01
    • Chih-Chiang TuHsin-Chang LeeJong-Yuh ChangChia-Jen ChenChun-Lang Chen
    • Chih-Chiang TuHsin-Chang LeeJong-Yuh ChangChia-Jen ChenChun-Lang Chen
    • G03F1/00G03F1/26G03F1/36G03F1/50
    • G03F1/36G03F1/50G03F1/58G03F1/80
    • Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.
    • 公开了掩模毛坯和掩模的结构,以及制造掩模的方法。 当过程经过蚀刻步骤三次时,新的掩模坯料和掩模包括三层蚀刻停止层,以防止损坏石英基板。 三重蚀刻停止层可以包括含有氮(TaN)的钽的第一子层,含有氧(TaO)的钽的第二子层和TaN的第三子层。 或者,三重蚀刻停止层可以包括SiON材料的第一子层,TaO材料的第二子层和SiON材料的第三子层。 另一个替代方案可以是一层低蚀刻速率的MoxSiyONz材料,当该工艺经过蚀刻步骤三次时,其可以防止对石英衬底的损坏。 通过使用各种光学邻近校正规则在掩模空白上定义岛掩模。
    • 3. 发明授权
    • Systems and methods for lithography masks
    • 光刻掩模的系统和方法
    • US08785083B2
    • 2014-07-22
    • US13486015
    • 2012-06-01
    • Chih-Chiang TuHsin-Chang LeeJong-Yuh ChangChia-Jen ChenChun-Lang Chen
    • Chih-Chiang TuHsin-Chang LeeJong-Yuh ChangChia-Jen ChenChun-Lang Chen
    • G03F1/00
    • G03F1/36G03F1/50G03F1/58G03F1/80
    • Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.
    • 公开了掩模毛坯和掩模的结构,以及制造掩模的方法。 当过程经过蚀刻步骤三次时,新的掩模坯料和掩模包括三层蚀刻停止层,以防止损坏石英基板。 三重蚀刻停止层可以包括含有氮(TaN)的钽的第一子层,含有氧(TaO)的钽的第二子层和TaN的第三子层。 或者,三重蚀刻停止层可以包括SiON材料的第一子层,TaO材料的第二子层和SiON材料的第三子层。 另一个替代方案可以是一层低蚀刻速率的MoxSiyONz材料,当该工艺经过蚀刻步骤三次时,其可以防止对石英衬底的损坏。 通过使用各种光学邻近校正规则在掩模空白上定义岛掩模。
    • 5. 发明申请
    • PHOTOVOLTAIC DEVICE MANUFACTURE
    • 光电器件制造
    • US20110318863A1
    • 2011-12-29
    • US12823667
    • 2010-06-25
    • Chih-Chiang TuChun-Lang Chen
    • Chih-Chiang TuChun-Lang Chen
    • H01L21/78H01L31/0224H01L31/032
    • H01L31/022425H01L31/03923H01L31/03928H01L31/0463H01L31/0749H01L31/18Y02E10/541Y02P70/521
    • A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.
    • 公开了一种光电器件制造方法。 方法包括使用纳米压印技术制造光伏电池来限定光伏器件的单个电池单元。 所述方法可以包括提供基底; 在所述衬底上形成第一导电层; 使用纳米压印和蚀刻工艺在第一导电层中形成第一凹槽; 在所述第一导电层上形成吸收层,所述吸收层填充在所述第一槽中; 使用纳米压印法在吸收层中形成第二凹槽; 在所述吸收层上形成第二导电层,所述第二导电层填充在所述第二槽中; 以及在所述第二导电层和所述吸收层中形成第三凹槽,从而限定光伏电池单元。
    • 6. 发明授权
    • Semiconductor mask blanks with a compatible stop layer
    • 具有兼容停止层的半导体掩模板
    • US08715890B2
    • 2014-05-06
    • US13362818
    • 2012-01-31
    • Chih-Chiang TuChun-Lang ChenBoming HsuTran-Hui Shen
    • Chih-Chiang TuChun-Lang ChenBoming HsuTran-Hui Shen
    • G03F1/00
    • H01L21/0332G03F1/26G03F1/46H01L21/0337H01L21/31H01L21/31116H01L22/26
    • Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.
    • 提供了一种用于创建包括停止层的掩模坯料的方法。 停止层是光学兼容的,并且与作为掩模坯料的一部分包括的其它层的工艺兼容。 这样的空白可以包括EUV,相移或OMOG掩模。 停止层包括钼,硅和氮化物,其比例允许相容性,并有助于残留气体分析仪的检测。 还提供了具有停止层的掩模坯料图案化的方法,特别是用于去除由于先前的掩模制造步骤中的问题而可能发生的半透明残留缺陷的方法。 该方法包括用残留气体分析仪检测包含的材料。 还提供了一种掩模空白结构,其结合了相容的停止层。
    • 7. 发明申请
    • PHOTOVOLTAIC CELL MANUFACTURE
    • 光电池制造
    • US20120003780A1
    • 2012-01-05
    • US12827213
    • 2010-06-30
    • Chih-Chiang TuChun-Lang Chen
    • Chih-Chiang TuChun-Lang Chen
    • H01L31/0236H01L31/18H01L31/0224
    • G03F7/0002B82Y10/00B82Y40/00H01L31/022425H01L31/022441H01L31/068H01L31/1804Y02E10/52Y02E10/547Y02P70/521
    • A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.
    • 公开了一种光伏电池的制造方法。 方法包括利用纳米压印技术制造具有选择性发射极和埋入接触(电极)结构的光伏电池。 所述方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底; 在所述半导体衬底中邻近所述第一表面形成第一掺杂区; 执行纳米压印工艺和蚀刻工艺以在所述半导体衬底中形成沟槽,所述沟槽从所述第一表面延伸到所述半导体衬底中; 在所述沟槽内的所述半导体衬底中形成第二掺杂区域,所述第二掺杂区域具有比所述第一掺杂区域更大的掺杂浓度; 并用导电材料填充沟槽。 纳米压印工艺使用模具来定义电极线布局的位置。
    • 8. 发明授权
    • Method for manufacturing photovoltaic device
    • 光伏器件制造方法
    • US08563351B2
    • 2013-10-22
    • US12823667
    • 2010-06-25
    • Chih-Chiang TuChun-Lang Chen
    • Chih-Chiang TuChun-Lang Chen
    • H01L21/00
    • H01L31/022425H01L31/03923H01L31/03928H01L31/0463H01L31/0749H01L31/18Y02E10/541Y02P70/521
    • A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.
    • 公开了一种光电器件制造方法。 方法包括使用纳米压印技术制造光伏电池来限定光伏器件的单个电池单元。 所述方法可以包括提供基底; 在所述衬底上形成第一导电层; 使用纳米压印和蚀刻工艺在所述第一导电层中形成第一凹槽; 在所述第一导电层上形成吸收层,所述吸收层填充在所述第一槽中; 使用纳米压印法在吸收层中形成第二凹槽; 在所述吸收层上形成第二导电层,所述第二导电层填充在所述第二槽中; 以及在所述第二导电层和所述吸收层中形成第三凹槽,从而限定光伏电池单元。
    • 9. 发明授权
    • Method for forming photovoltaic cell
    • 光电池形成方法
    • US08293645B2
    • 2012-10-23
    • US12827213
    • 2010-06-30
    • Chih-Chiang TuChun-Lang Chen
    • Chih-Chiang TuChun-Lang Chen
    • H01L21/44
    • G03F7/0002B82Y10/00B82Y40/00H01L31/022425H01L31/022441H01L31/068H01L31/1804Y02E10/52Y02E10/547Y02P70/521
    • A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.
    • 公开了一种光伏电池的制造方法。 方法包括利用纳米压印技术制造具有选择性发射极和埋入接触(电极)结构的光伏电池。 所述方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底; 在所述半导体衬底中邻近所述第一表面形成第一掺杂区; 执行纳米压印工艺和蚀刻工艺以在所述半导体衬底中形成沟槽,所述沟槽从所述第一表面延伸到所述半导体衬底中; 在所述沟槽内的所述半导体衬底中形成第二掺杂区域,所述第二掺杂区域具有比所述第一掺杂区域更大的掺杂浓度; 并用导电材料填充沟槽。 纳米压印工艺使用模具来定义电极线布局的位置。