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    • 6. 发明申请
    • Method for Generating Images of Multi-Views
    • 多视图生成方法
    • US20120020548A1
    • 2012-01-26
    • US12948957
    • 2010-11-18
    • Meng-Chao KAOChien-Hung CHENTzu-Chiang SHEN
    • Meng-Chao KAOChien-Hung CHENTzu-Chiang SHEN
    • G06K9/00
    • G06T15/205H04N13/261
    • The present invention provides a method for generating images of multi-views. The method includes obtaining a 2D original image of an article and background figures of multi-views; calculating the background image range and the main body image range of the 2D original image of the article; cutting the main body image out; generating a depth model according to an equation; cutting the depth model according to the main body image range of the cut 2D image of the article; shifting every pixel in the main body image of the 2D original image of the article according to the cut depth model to obtain shifted main body images of multi-views; and synthesizing the shifted main body images of multi-views and the background figures of multi-views to obtain the final images of multi-views for 3D image reconstruction.
    • 本发明提供一种生成多视图图像的方法。 该方法包括获得文章的2D原始图像和多视图的背景图; 计算文章的2D原始图像的背景图像范围和主体图像范围; 切割主体图像; 根据等式生成深度模型; 根据文章切割2D图像的主体图像范围切割深度模型; 根据切割深度模型移动物品的2D原始图像的主体图像中的每个像素,以获得多视角的偏移主体图像; 并合成多视角的偏移主体图像和多视点的背景图,以获得用于3D图像重建的多视图的最终图像。
    • 8. 发明申请
    • FLIP-FLOP CIRCUIT, FREQUENCY DIVIDER AND FREQUENCY DIVIDING METHOD
    • FLIP-FLOP电路,频率分频器和频率分割方法
    • US20130187686A1
    • 2013-07-25
    • US13569568
    • 2012-08-08
    • Min-Shueh YUANChien-Hung CHENShao-Yu LI
    • Min-Shueh YUANChien-Hung CHENShao-Yu LI
    • H03B19/12H03K19/096
    • H03K3/0375
    • In response to a first level of the clock signal, an inverting output of a flip-flop circuit is connected, via a non-inverting input thereof, to a first intermediate node of the flip-flop circuit and a non-inverting output of the flip-flop circuit is connected, via an inverting input thereof, to a second intermediate node of the flip-flop circuit. In response to a second level of the clock signal, the first intermediate node is connected, via a third intermediate node of the flip-flop circuit, to the non-inverting output and the second intermediate node is connected, via a fourth intermediate node of the flip-flop circuit, to the inverting output. A first cross-coupled gates arrangement of the flip-flop circuit is coupled between the first and second intermediate nodes. A second cross-coupled gates arrangement of the flip-flop circuit is coupled between the third and fourth intermediate nodes.
    • 响应于第一级时钟信号,触发器电路的反相输出经由其非反相输入连接到触发器电路的第一中间节点,并且该反相输出端 触发器电路经由其反相输入连接到触发器电路的第二中间节点。 响应于时钟信号的第二电平,第一中间节点经由触发器电路的第三中间节点连接到非反相输出端,并且第二中间节点经由第四中间节点 触发器电路,到反相输出。 触发器电路的第一交叉耦合门装置耦合在第一和第二中间节点之间。 触发器电路的第二交叉耦合栅极布置耦合在第三和第四中间节点之间。
    • 10. 发明申请
    • NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF
    • 非易失性存储器及其制造方法
    • US20120018795A1
    • 2012-01-26
    • US12843093
    • 2010-07-26
    • Chien-Hung CHENTzu-Ping ChenYu-Jen Chang
    • Chien-Hung CHENTzu-Ping ChenYu-Jen Chang
    • H01L29/792H01L21/336
    • H01L29/792H01L21/28282H01L27/11573H01L29/4234H01L29/66833
    • A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening.
    • 公开了一种非易失性存储器的制造方法。 栅极结构形成在衬底上,并且包括栅极介电层和栅极导电层。 部分地去除栅介质层,从而在栅极导电层,基板和栅极电介质层之间形成对称的开口,并且在栅极电介质层的端侧形成空腔。 在栅极导电层的侧壁和底部上形成第一氧化物层,并且在衬底的表面上形成第二氧化物层。 形成覆盖栅极结构,第一和第二氧化物层和衬底并填充开口的氮化物材料层。 执行蚀刻处理以部分地去除氮化物材料层,由此在栅极导电层的侧壁上形成并延伸到开口中的氮化物层。