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1. 发明授权

US08662917B2 Cable assembly having an improved circuit board 有权
标题翻译：电缆组件具有改进的电路板
公开(公告)号：US08662917B2
公开(公告)日：2014-03-04
申请号：US13314468
申请日：2011-12-08
申请人： Chien-Chiung Wang , Xue-Liang Zhang , Qing-Man Zhu , Jian-Jun Zhu
发明人： Chien-Chiung Wang , Xue-Liang Zhang , Qing-Man Zhu , Jian-Jun Zhu
IPC分类号： H01R12/24
CPC分类号： H01R13/6658 , H01R9/038 , H01R12/515 , H01R13/502
摘要： A cable assembly (100) includes a cover (40) defining a cavity (101), a circuit board (20) assembled in the cavity and including a first surface (201) and a second surface (202) lower than the first surface, and a cable (2) having a jacket (22) and a number of wires (21) shrouded by the jacket. Each wire includes an inner coat (210) and a conductor having a free end (211) exposed outwardly from the inner coat for being soldered to the first surface, with the inner coat disposed on the second surface.
摘要翻译：电缆组件（100）包括限定空腔（101）的盖子（40），组装在空腔中并包括第一表面（201）和低于第一表面的第二表面（202）的电路板（20）以及具有护套（22）的电缆（2）和由护套覆盖的多个电线（21）。每个线包括内涂层（210）和具有从内涂层向外暴露的自由端（211）的导体，用于焊接到第一表面，内涂层设置在第二表面上。

2. 发明授权

US08597045B2 Transceiver connector having improved collar clip 有权
标题翻译：收发器连接器具有改进的卡圈夹
公开(公告)号：US08597045B2
公开(公告)日：2013-12-03
申请号：US13432285
申请日：2012-03-28
申请人： Jian-Jun Zhu , Qing-Man Zhu , Chien-Chiung Wang
发明人： Jian-Jun Zhu , Qing-Man Zhu , Chien-Chiung Wang
IPC分类号： H01R13/627
CPC分类号： H01R13/6271 , H01R13/506 , H01R13/6582
摘要： A transceiver connector (100) includes a housing (1) having a number of faces including a primary face (10) and a pair of side faces (13) and a collar clip (2). The collar clip includes a base at least partially surrounding the plurality of faces of the housing. The primary face defines at least one vertically extending locking recess (104) having a stepped portion (1041). The collar clip includes a base (20) at least partially surrounding the number of faces of the housing. The base includes at least one locking beam (204) inserted into the corresponding locking recess of the housing along a first direction and having a click portion (2041) engaging with the stepped portion of the housing along a second direction perpendicular to the first direction.
摘要翻译：收发器连接器（100）包括具有包括主面（10）和一对侧面（13）和套圈夹（2）的多个面的壳体（1）。套环夹具包括至少部分地围绕壳体的多个面的基部。主面限定具有阶梯部分（1041）的至少一个垂直延伸的锁定凹部（104）。套环夹具包括至少部分地围绕壳体的多个面的基座（20）。底座包括沿着第一方向插入壳体的相应的锁定凹部中的至少一个锁定梁（204），并且具有与垂直于第一方向的第二方向与壳体的阶梯部分接合的咔嗒部分（2041）。

3. 发明授权

US08500470B2 Plug connector having a releasing mechanism and a connector assembly having the same 有权
标题翻译：具有释放机构的插头连接器和具有该释放机构的连接器组件
公开(公告)号：US08500470B2
公开(公告)日：2013-08-06
申请号：US13335233
申请日：2011-12-22
申请人： Chien-Chiung Wang , Qing-Man Zhu , Jian-Jun Zhu , Jerry Wu
发明人： Chien-Chiung Wang , Qing-Man Zhu , Jian-Jun Zhu , Jerry Wu
IPC分类号： H01R13/62
CPC分类号： G02B6/4261 , G02B6/3898
摘要： A connector assembly includes a receptacle (200) having a latching tab (2) defining a latching hole (21) and a plug connector (100). The plug connector includes a housing (1) having a latching nose (111) for latching with the latching hole and a releasing mechanism. The releasing mechanism includes two resisting beams (53) disposed on the housing and having two protrusions (531), a puller (71), and an operator (72) having two guiding portions (722) projecting toward and in front of the protrusions. The guiding portions slide beneath the protrusions, in response to a rearward movement of the puller, to tilt the resisting beams upwardly and lift the latching tab from a latched position to a released position for releasing the latching nose from the latching hole.
摘要翻译：连接器组件包括具有限定锁定孔（21）和插头连接器（100）的闩锁突片（2）的插座（200）。插头连接器包括具有用于与闩锁孔锁定的闩锁鼻部（111）和释放机构的壳体（1）。释放机构包括设置在壳体上的两个阻力梁（53），具有两个突起（531），一个牵引器（71）和一个操作器（72），该突起部分（72）具有突出部分和突出部分的两个引导部分（722）。引导部分响应于拉动器的向后移动而滑动在突起下方，以使抵抗梁向上倾斜，并将闩锁突出部从闩锁位置提升到释放位置，以将闩锁鼻部从闩锁孔释放。

4. 发明授权

US08864506B2 Cable connector with improved grounding plate 有权
标题翻译：带改进接地板的电缆连接器
公开(公告)号：US08864506B2
公开(公告)日：2014-10-21
申请号：US13783403
申请日：2013-03-04
申请人： Terrance F. Little , An-Jen Yang , Stephen Sedio , Richard Lee Malehorn, II , Chien-Ping Kao , Kuo-Chun Hsu , Wei-Hung Hsu , Qing-Man Zhu , Jian-Jun Zhu , Li-Shing Hou
发明人： Terrance F. Little , An-Jen Yang , Stephen Sedio , Richard Lee Malehorn, II , Chien-Ping Kao , Kuo-Chun Hsu , Wei-Hung Hsu , Qing-Man Zhu , Jian-Jun Zhu , Li-Shing Hou
IPC分类号： H01R13/648 , H01R13/658
CPC分类号： H01R13/658 , H01R13/6585
摘要： A cable connector includes an insulative housing including two sidewalls and a mating slot defined between the two sidewalls, and a plurality of terminals received in the insulative housing. The terminals include contacting portions exposed to the mating slot and connecting portions behind a rear end of the insulating housing. The two sidewalls are loaded with a first row and a second row of the plurality of terminals respectively. The first row includes signal terminals and grounding terminals. A grounding plate is inserted in the insulating housing and between two rows of terminals. The grounding plate defines resilient arms and connecting legs, the resilient arms slant to the first row and touch with the grounding terminals.
摘要翻译：电缆连接器包括绝缘壳体，其包括两个侧壁和限定在两个侧壁之间的配合槽，以及容纳在绝缘壳体中的多个端子。端子包括暴露于配合槽的接触部分和绝缘壳体的后端后面的连接部分。两个侧壁分别装载有多个端子的第一排和第二排。第一行包括信号端子和接地端子。接地板插入绝缘外壳和两排端子之间。接地板限定弹性臂和连接腿，弹性臂倾斜到第一排并与接地端接触。

5. 发明申请

US20060143320A1 SYSTEM AND METHOD FOR CHECKING DRIVERS OF HARDWARE DEVICES OF A COMPUTER 审中-公开
标题翻译：用于检查计算机硬件设备驱动程序的系统和方法
公开(公告)号：US20060143320A1
公开(公告)日：2006-06-29
申请号：US11163900
申请日：2005-11-03
申请人： Jian-Jun Zhu , Ping-Hui Chen
发明人： Jian-Jun Zhu , Ping-Hui Chen
IPC分类号： G06F3/00
CPC分类号： G06F9/4411 , G06F11/26
摘要： The present invention provides a system for checking drivers of hardware devices of a computer (10). The system includes: a traveling module (101) for traveling a tree structure of the drivers by accessing the System Regedit of the computer through an application programming interface; a retrieving module (102) for retrieving an error code for each of the drivers and contents of an initialization file which includes information on a version of each of the drivers; and a determining module (103) for determining whether a driver is installed properly according to the corresponding error code, and for determining whether the driver has a correct version according to the contents of the initialization file. A related method is also provided.
摘要翻译：本发明提供了一种用于检查计算机（10）的硬件设备的驱动程序的系统。该系统包括：行进模块（101），用于通过应用编程接口访问计算机的系统重新定位来行进驾驶员的树形结构; 用于检索每个驱动程序的错误代码和初始化文件的内容的检索模块（102），其包括关于每个驱动程序的版本的信息; 以及确定模块（103），用于根据相应的错误代码确定驱动程序是否正确安装，以及根据初始化文件的内容确定驱动程序是否具有正确的版本。还提供了相关的方法。

6. 发明申请

US20060197869A1 APPARATUS AND METHOD FOR ADJUSTING A PIXEL CLOCK FREQUENCY BASED ON A PHASE LOCKED LOOP 失效
标题翻译：基于相位锁定环路调整像素时钟频率的装置和方法
公开(公告)号：US20060197869A1
公开(公告)日：2006-09-07
申请号：US11306444
申请日：2005-12-28
申请人： Jian-Feng Wang , Jian-Jun Zhu , Liang-Yan Dai
发明人： Jian-Feng Wang , Jian-Jun Zhu , Liang-Yan Dai
IPC分类号： H04N5/06 , H03L7/00
CPC分类号： H04N5/126 , H03L7/18
摘要： An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL) includes: a pixel clock generator (11) for generating an actual pixel clock having an actual frequency; a division frequency counter (12) for dividing the actual pixel clock into several pixel clocks having different frequency ranges by means of multiplying the actual frequency of the actual pixel clock by a multiplier; a reference frequency counter (13) for dividing the actual pixel clock by means of lowering the actual frequency of the actual pixel clock, and generating a reference frequency; a reactive frequency counter (14) for dividing the actual pixel clock by means of heightening the actual frequency of the actual pixel clock, and generating a reactive frequency; a PLL circuit (16) for integrating the reference frequency and the reactive frequency to generate a required pixel clock having a required frequency. A related method is also disclosed.
摘要翻译：一种用于基于锁相环（PLL）调整像素时钟频率的装置，包括：用于产生具有实际频率的实际像素时钟的像素时钟发生器（11）分频计数器，用于通过将实际像素时钟的实际频率乘以乘数，将实际像素时钟划分成具有不同频率范围的几个像素时钟; 用于通过降低实际像素时钟的实际频率并且产生参考频率来划分实际像素时钟的参考频率计数器（13）用于通过提高实际像素时钟的实际频率并产生无功频率来分割实际像素时钟的无功频率计数器（14）用于对基准频率和无功频率进行积分以产生具有所需频率的所需像素时钟的PLL电路（16）。还公开了相关方法。

7. 发明授权

US07561205B2 Apparatus and method for adjusting a pixel clock frequency based on a phase locked loop 失效
标题翻译：基于锁相环调整像素时钟频率的装置和方法
公开(公告)号：US07561205B2
公开(公告)日：2009-07-14
申请号：US11306444
申请日：2005-12-28
申请人： Jian-Feng Wang , Jian-Jun Zhu , Liang-Yan Dai
发明人： Jian-Feng Wang , Jian-Jun Zhu , Liang-Yan Dai
IPC分类号： H04N5/06
CPC分类号： H04N5/126 , H03L7/18
摘要： An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL) includes: a pixel clock generator (11) for generating an actual pixel clock having an actual frequency; a division frequency counter (12) for dividing the actual pixel clock into several pixel clocks having different frequency ranges by means of multiplying the actual frequency of the actual pixel clock by a multiplier; a reference frequency counter (13) for dividing the actual pixel clock by means of lowering the actual frequency of the actual pixel clock, and generating a reference frequency; a reactive frequency counter (14) for dividing the actual pixel clock by means of heightening the actual frequency of the actual pixel clock, and generating a reactive frequency; a PLL circuit (16) for integrating the reference frequency and the reactive frequency to generate a required pixel clock having a required frequency. A related method is also disclosed.
摘要翻译：一种用于基于锁相环（PLL）调整像素时钟频率的装置，包括：用于产生具有实际频率的实际像素时钟的像素时钟发生器（11）分频计数器，用于通过将实际像素时钟的实际频率乘以乘数，将实际像素时钟划分成具有不同频率范围的几个像素时钟; 用于通过降低实际像素时钟的实际频率并且产生参考频率来划分实际像素时钟的参考频率计数器（13）用于通过提高实际像素时钟的实际频率并产生无功频率来分割实际像素时钟的无功频率计数器（14）用于对基准频率和无功频率进行积分以产生具有所需频率的所需像素时钟的PLL电路（16）。还公开了相关方法。

8. 发明申请

US20060227127A1 VIDEO GRAPHIC ARRAY COLORFUL SIGNAL GENERATOR 失效
标题翻译：视频图形彩色信号发生器
公开(公告)号：US20060227127A1
公开(公告)日：2006-10-12
申请号：US11308152
申请日：2006-03-08
申请人： Jian-Feng Wang , Jian-Jun Zhu , Liang-Yan Dai
发明人： Jian-Feng Wang , Jian-Jun Zhu , Liang-Yan Dai
IPC分类号： G09G5/00
CPC分类号： G09G5/20 , G09G3/006 , G09G5/18 , G09G2360/02 , H04N17/02
摘要： A video graphic array colorful signal generator is provided. The signal generator includes a FPGA (field program gate array) device (1), a PROM (programmable read only memory) (2), a PLL (phase locked loop) circuit (3), a D/A (digital/analog) convertor (4) connected with the FPGA device, a VGA (video graphic array) interface (5), a pixel clock generator (6) which generates pixel clock continuously at a frequency, and a keyboard (7) which provides operating buttons for users.
摘要翻译：提供了一个视频图形阵列彩色信号发生器。信号发生器包括FPGA（现场编程门阵列）器件（1），PROM（可编程只读存储器）（2），PLL（锁相环）电路（3），D / A（数字/模拟）转换器（4），VGA（视频图形阵列）接口（5），以频率连续生成像素时钟的像素时钟发生器（6）和为用户提供操作按钮的键盘（7）。

9. 发明申请

US20060107162A1 System and method for checking BIOS ROM data 失效
标题翻译：检查BIOS ROM数据的系统和方法
公开(公告)号：US20060107162A1
公开(公告)日：2006-05-18
申请号：US11249301
申请日：2005-10-13
申请人： Liang-Yan Dai , Jian-Jun Zhu
发明人： Liang-Yan Dai , Jian-Jun Zhu
IPC分类号： H04L1/00 , H03M13/00 , G08C25/00 , G06F11/00 , G06F11/30
CPC分类号： G06F11/1004
摘要： A system for checking BIOS ROM data is disclosed. The system includes a keyboard (10), a display (20), a computer host (30), and a checking device (40). The computer host (30) has a BIOS ROM (301) installed therein. The checking device (40) includes: a data dividing module (400) for dividing the BIOS ROM data into a plurality of sections; a data obtaining module (401) for capturing BIOS ROM data from one or more sections, and for counting a check datum; a data checking module (402) for comparing the check datum with a standard datum, and for determining whether the two data are equal; and a checking result outputting module (403) for outputting the checking results. A related method is also disclosed.
摘要翻译：公开了一种用于检查BIOS ROM数据的系统。该系统包括键盘（10），显示器（20），计算机主机（30）和检查装置（40）。计算机主机（30）具有安装在其中的BIOS ROM（301）。检查装置（40）包括：数据划分模块（400），用于将BIOS ROM数据分割成多个部分; 用于从一个或多个部分捕获BIOS ROM数据并用于计数检查数据的数据获取模块（401）数据检查模块（402），用于将检查数据与标准数据进行比较，并用于确定两个数据是否相等; 以及用于输出检查结果的检查结果输出模块（403）。还公开了相关方法。

10. 发明授权

US07543222B2 System and method for checking BIOS ROM data 失效
标题翻译：检查BIOS ROM数据的系统和方法
公开(公告)号：US07543222B2
公开(公告)日：2009-06-02
申请号：US11249301
申请日：2005-10-13
申请人： Liang-Yan Dai , Jian-Jun Zhu
发明人： Liang-Yan Dai , Jian-Jun Zhu
IPC分类号： G06F7/02
CPC分类号： G06F11/1004
摘要： A system for checking basic input output system read only memory (BIOS ROM) data includes a keyboard, a display, a computer host, and a checking device. The computer host has a BIOS ROM installed therein. The checking device includes: a data dividing module for dividing the BIOS ROM data into a plurality of sections; a data obtaining module for capturing BIOS ROM data from one or more sections, and for counting a check datum; a data checking module for comparing the check datum with a standard datum, and for determining whether the two data are equal; and a checking result outputting module for outputting the checking results.
摘要翻译：用于检查基本输入输出系统只读存储器（BIOS ROM）数据的系统包括键盘，显示器，计算机主机和检查装置。计算机主机上安装有一个BIOS ROM。检查装置包括：数据分割模块，用于将BIOS ROM数据分割成多个部分; 用于从一个或多个部分捕获BIOS ROM数据并用于计数检查数据的数据获取模块; 数据检查模块，用于将检查数据与标准数据进行比较，并确定两个数据是否相等; 以及检查结果输出模块，用于输出检查结果。

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