专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07342289B2 Strained silicon MOS devices 有权
标题翻译：应变硅MOS器件
公开(公告)号：US07342289B2
公开(公告)日：2008-03-11
申请号：US10637351
申请日：2003-08-08
申请人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
发明人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.
摘要翻译：一种提高集成电路中MOS器件的载流子迁移率的结构。该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

2. 发明申请

US20050116360A1 Complementary field-effect transistors and methods of manufacture 审中-公开
标题翻译：互补场效应晶体管及其制造方法
公开(公告)号：US20050116360A1
公开(公告)日：2005-06-02
申请号：US10896270
申请日：2004-07-21
申请人： Chien-Chao Huang , Fu-Liang Yang , Mickey Ken , Chenming Hu , Chung-Hu Ge , Wen-Chin Lee , Chih-Hsin Ko
发明人： Chien-Chao Huang , Fu-Liang Yang , Mickey Ken , Chenming Hu , Chung-Hu Ge , Wen-Chin Lee , Chih-Hsin Ko
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L31/0328
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/045 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.
摘要翻译：提供互补的FET和制造方法。互补FET使用具有<100>晶体取向的表面层的衬底。通过硅化源极/漏极区域，拉伸应力膜，浅沟槽隔离层，层间电介质等添加了提高NMOS FET的性能的拉伸应力。

3. 发明申请

US20050032321A1 Strained silicon MOS devices 有权
标题翻译：应变硅MOS器件
公开(公告)号：US20050032321A1
公开(公告)日：2005-02-10
申请号：US10637351
申请日：2003-08-08
申请人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos Diaz , Fu-Liang Yang
发明人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos Diaz , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.
摘要翻译：一种提高集成电路中MOS器件的载流子迁移率的结构。该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

4. 发明授权

US06867433B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
标题翻译：包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
公开(公告)号：US06867433B2
公开(公告)日：2005-03-15
申请号：US10426566
申请日：2003-04-30
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
摘要翻译：根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

5. 发明申请

US20050093067A1 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
公开(公告)号：US20050093067A1
公开(公告)日：2005-05-05
申请号：US10999564
申请日：2004-11-29
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

6. 发明授权

US07268024B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
标题翻译：包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
公开(公告)号：US07268024B2
公开(公告)日：2007-09-11
申请号：US10999564
申请日：2004-11-29
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
摘要翻译：根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

7. 发明授权

US07141459B2 Silicon-on-insulator ULSI devices with multiple silicon film thicknesses 有权
标题翻译：具有多个硅膜厚度的绝缘体上硅ULSI器件
公开(公告)号：US07141459B2
公开(公告)日：2006-11-28
申请号：US10388297
申请日：2003-03-12
申请人： Fu-Liang Yang , Hao-Yu Chen , Yee-Chia Yeo , Carlos H. Diaz , Chenming Hu
发明人： Fu-Liang Yang , Hao-Yu Chen , Yee-Chia Yeo , Carlos H. Diaz , Chenming Hu
IPC分类号： H01L21/84 , H01L21/00 , H01L21/36 , H01L21/8238
CPC分类号： H01L21/7624 , H01L21/84 , H01L27/1203
摘要： A method of forming a multiple-thickness semiconductor-on-insulator, comprising the following steps. A wafer is provided comprising a semiconductor film (having at least two regions) overlying a buried insulator layer overlying a substrate. The semiconductor film within one of the at least two regions is masked to provide at least one semiconductor film masked portion having a first thickness, leaving exposed the semiconductor film within at least one of the at least two regions to provide at least one semiconductor film exposed portion having the first thickness. In one embodiment, at least a portion of the at least one exposed semiconductor film portion is oxidized to provide at least one partially oxidized, exposed semiconductor film portion. Then the oxidized portion of the exposed semiconductor film is removed to leave a portion of the semiconductor film having a second thickness less than the first thickness.
摘要翻译：一种形成多层绝缘体半导体的方法，包括以下步骤。提供晶片，其包括覆盖在衬底上的掩埋绝缘体层的半导体膜（具有至少两个区域）。至少两个区域之一内的半导体膜被掩模以提供具有第一厚度的至少一个半导体膜掩模部分，使半导体膜暴露在至少两个区域中的至少一个区域中，以提供至少一个半导体膜暴露具有第一厚度的部分。在一个实施例中，所述至少一个暴露的半导体膜部分的至少一部分被氧化以提供至少一个部分氧化的暴露的半导体膜部分。然后去除暴露的半导体膜的氧化部分，以留下具有小于第一厚度的第二厚度的半导体膜的一部分。

8. 发明授权

US07357838B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US07357838B2
公开(公告)日：2008-04-15
申请号：US11074738
申请日：2005-03-08
申请人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B23/00
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.
摘要翻译：提供了在松弛的低缺陷密度半导体合金层（例如SiGe）上形成应变硅层的方法。

9. 发明授权

US07183137B2 Method for dicing semiconductor wafers 有权
标题翻译：切割半导体晶片的方法
公开(公告)号：US07183137B2
公开(公告)日：2007-02-27
申请号：US10725697
申请日：2003-12-01
申请人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
发明人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/50 , H01L21/78
CPC分类号： H01L21/78 , B28D5/00
摘要： A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.
摘要翻译：公开了一种用于切割具有金刚石结构的基底材料的晶片的方法。晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。

10. 发明授权

US06878610B1 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US06878610B1
公开(公告)日：2005-04-12
申请号：US10228545
申请日：2002-08-27
申请人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/36 , H01L21/84 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.
摘要翻译：已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理允许为SiGe层实现优化的弛豫和缺陷密度。在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的，低缺陷密度SiGe层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式