专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050133896A1 Semiconductor package with a flip chip on a solder-resist leadframe 有权
标题翻译：半导体封装在阻焊引线框上具有倒装芯片
公开(公告)号：US20050133896A1
公开(公告)日：2005-06-23
申请号：US11014165
申请日：2004-12-17
申请人： Chien Liu , Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Tai-Yuan Huang
发明人： Chien Liu , Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Tai-Yuan Huang
IPC分类号： H01L23/31 , H01L23/433 , H01L23/495 , H01L23/48
CPC分类号： H01L24/17 , H01L23/3107 , H01L23/4334 , H01L23/49548 , H01L23/49558 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/13099 , H01L2224/16245 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/16152 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “Ω”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.
摘要翻译：半导体封装包括安装在多个引线上并由模塑料封装的倒装芯片。引线的上表面在引线的扇入端处包括多个凸起接合区域，并且引线的下表面在引线的扇出端处包括多个外连接区域。在引线的上表面和相邻的凸起焊接区域附近形成多个压痕，以避免引线上的焊料污染。成型后，用模塑料填充压痕。优选地，凹痕具有反转的“Ω”形轮廓，以防止倒装芯片的凸起在引线的其它部分上过度润湿以牢固地固定引线的扇形端。

2. 发明授权

US07253508B2 Semiconductor package with a flip chip on a solder-resist leadframe 有权
标题翻译：半导体封装在阻焊引线框上具有倒装芯片
公开(公告)号：US07253508B2
公开(公告)日：2007-08-07
申请号：US11014165
申请日：2004-12-17
申请人： Chien Liu , Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Tai-Yuan Huang
发明人： Chien Liu , Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Tai-Yuan Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/17 , H01L23/3107 , H01L23/4334 , H01L23/49548 , H01L23/49558 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/13099 , H01L2224/16245 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/16152 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “Ω”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.
摘要翻译：半导体封装包括安装在多个引线上并由模塑料封装的倒装芯片。引线的上表面在引线的扇入端处包括多个凸起接合区域，并且引线的下表面在引线的扇出端处包括多个外连接区域。在引线的上表面和相邻的凸起焊接区域附近形成多个压痕，以避免引线上的焊料污染。成型后，用模塑料填充压痕。优选地，凹痕具有反转的“Ω”形轮廓，以防止倒装芯片的凸起在引线的其它部分上过度润湿以牢固地固定引线的扇形端。

3. 发明申请

US20050101053A1 Quad flat flip chip packaging process and leadframe therefor 有权
标题翻译：四平面倒装芯片封装工艺及其引线框架
公开(公告)号：US20050101053A1
公开(公告)日：2005-05-12
申请号：US10967910
申请日：2004-10-18
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/31 , H01L23/495 , H01L21/48
CPC分类号： H01L23/49558 , H01L23/3114 , H01L23/49586 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2224/05599
摘要： A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.
摘要翻译：提供了一种四平面倒装芯片封装工艺及其引线框架。牺牲膜附着在引线框架的引线上，用于在形成时限制凸块的程度并节省制造成本。此外，在回流步骤之后，牺牲膜可以从引线框架移除。因此，可以在成型步骤期间防止模塑料和导线之间的分层。

4. 发明授权

US07067904B2 Flip-chip type quad flat package and leadframe 有权
标题翻译：倒装片式四方扁平封装和引线框架
公开(公告)号：US07067904B2
公开(公告)日：2006-06-27
申请号：US10979881
申请日：2004-11-01
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Chien Liu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Chien Liu
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/4952 , H01L23/49541 , H01L23/49568 , H01L2224/05571 , H01L2224/05573 , H01L2224/16
摘要： A flip-chip type quad flat package and a leadframe. The leadframe comprises a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.
摘要翻译：倒装型四边形扁平封装和引线框架。引线框架包括凸块连接区域和非连接区域。突起连接区域的最大宽度大于非连接区域的宽度。在进行回流处理之后，凸块被限制在凸块连接区域，从而防止凸块塌陷，制造成本降低，工艺简化。

5. 发明授权

US07022551B2 Quad flat flip chip packaging process and leadframe therefor 有权
标题翻译：四平面倒装芯片封装工艺及其引线框架
公开(公告)号：US07022551B2
公开(公告)日：2006-04-04
申请号：US10967910
申请日：2004-10-18
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L21/44
CPC分类号： H01L23/49558 , H01L23/3114 , H01L23/49586 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2224/05599
摘要： A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.
摘要翻译：提供了一种四平面倒装芯片封装工艺及其引线框架。牺牲膜附着在引线框架的引线上，用于在形成时限制凸块的程度并节省制造成本。此外，在回流步骤之后，牺牲膜可以从引线框架移除。因此，可以在成型步骤期间防止模塑料和引线之间的分层。

6. 发明申请

US20050104167A1 Flip-chip type quad flat package and leadframe 有权
标题翻译：倒装片式四方扁平封装和引线框架
公开(公告)号：US20050104167A1
公开(公告)日：2005-05-19
申请号：US10979881
申请日：2004-11-01
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Chien Liu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Chien Liu
IPC分类号： H01L23/31 , H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/4952 , H01L23/49541 , H01L23/49568 , H01L2224/05571 , H01L2224/05573 , H01L2224/16
摘要： A flip-chip type quad flat package and a leadframe. The leadframe comprsies a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.
摘要翻译：倒装型四边形扁平封装和引线框架。引线框架包括凸块连接区域和非连接区域。突起连接区域的最大宽度大于非连接区域的宽度。在进行回流处理之后，凸块被限制在凸块连接区域，从而防止凸块塌陷，制造成本降低，工艺简化。

7. 发明授权

US07164202B2 Quad flat flip chip package and leadframe thereof 有权
标题翻译：四平面倒装芯片封装及其引线框架
公开(公告)号：US07164202B2
公开(公告)日：2007-01-16
申请号：US10904517
申请日：2004-11-15
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/48
CPC分类号： H01L23/49551 , H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01322 , H01L2924/18161 , H01L2224/05599
摘要： A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.
摘要翻译：提供了四平面倒装芯片封装及其引线框。通过弯曲或蚀刻引线框架的引线来限定凸块连接部分。因此，在回流焊接工序之后形成的凸点被限制在凸块连接部内，并且可以防止凸块的塌陷。此外，可以减少包装的制造成本，并且可以简化其处理。

8. 发明申请

US20050156296A1 QUAD FLAT FLIP CHIP PACKAGE AND LEADFRAME THEREOF 有权
标题翻译：四边形平板纸芯片包装和铅笔
公开(公告)号：US20050156296A1
公开(公告)日：2005-07-21
申请号：US10904517
申请日：2004-11-15
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/31 , H01L23/433 , H01L23/495
CPC分类号： H01L23/49551 , H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01322 , H01L2924/18161 , H01L2224/05599
摘要： A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.
摘要翻译：提供了四平面倒装芯片封装及其引线框。通过弯曲或蚀刻引线框架的引线来限定凸块连接部分。因此，在回流焊接工序之后形成的凸点被限制在凸块连接部内，并且可以防止凸块的塌陷。此外，可以减少包装的制造成本，并且可以简化其处理。

9. 发明授权

US06967403B2 Package structure with a heat spreader and manufacturing method thereof 有权
标题翻译：散热器的包装结构及其制造方法
公开(公告)号：US06967403B2
公开(公告)日：2005-11-22
申请号：US10872190
申请日：2004-06-18
申请人： Chi-Ta Chuang , Chih-Min Pao , Chien Liu , Chi-Hao Chiu
发明人： Chi-Ta Chuang , Chih-Min Pao , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/36 , H01L23/552 , H01L23/34
CPC分类号： H01L23/552 , H01L23/36 , H01L2224/16225 , H01L2224/73253 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H01L2924/3025 , H01L2224/0401
摘要： A package structure with a heat spreader and manufacturing method thereof is disclosed. The package structure includes a substrate, a ground pad, a heat spreader, a non-conductive adhesive layer, and a pre-solder layer. A die is seated on the substrate, and the ground pad is disposed on the surface of the substrate. The manufacturing method of the package structure includes the following steps: (a) providing the substrate; (b) forming the pre-solder layer on the ground pad by solder paste printing; (c) forming the non-conductive adhesive layer on the substrate surface for being adjacent to the pre-solder layer by adhesive dispensing; (d) disposing the heat spreader onto the non-conductive layer and the pre-solder layer; and (e) heating the non-conductive adhesive layer for solidification and continuing to heat the pre-solder layer for solder reflow so that the heat spreader is adhered to the substrate via the non-conductive adhesive layer and coupled to the ground pad via the pre-solder layer.
摘要翻译：公开了具有散热器的封装结构及其制造方法。封装结构包括衬底，接地垫，散热器，非导电粘合剂层和预焊料层。模具坐在基板上，接地垫设置在基板的表面上。封装结构的制造方法包括以下步骤：（a）提供衬底; （b）通过焊膏印刷在接地焊盘上形成预焊料层; （c）通过粘合剂分配在所述基板表面上形成与所述预焊料层相邻的所述非导电粘合剂层; （d）将散热器设置在非导电层和预焊料层上; 和（e）加热不导电粘合剂层以进行固化，并继续加热用于焊料回流的预焊料层，使得散热器经由非导电粘合剂层粘合到基板上，并经由预焊层。

10. 发明授权

US07425468B2 Method for making flip chip on leadframe package 有权
标题翻译：在引线框封装上制作倒装芯片的方法
公开(公告)号：US07425468B2
公开(公告)日：2008-09-16
申请号：US11636995
申请日：2006-12-12
申请人： Meng-Jen Wang , Chien Liu , Tsan-Sheng Huang
发明人： Meng-Jen Wang , Chien Liu , Tsan-Sheng Huang
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/10135 , H01L2224/1147 , H01L2224/1181 , H01L2224/13099 , H01L2224/81011 , H01L2224/81136 , H01L2224/81139 , H01L2224/81194 , H01L2224/8121 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322
摘要： A flip chip on leadframe package and manufacturing method includes providing a leadframe having a plurality of inner leads; providing a chip having an active surface; forming a plurality of first bumps and at least one second bump on the active surface, the material of the first bumps is the same as the second bump, and the height of the second bump is lower than the first bumps; dipping the top of the first bumps in a flux, so that the second bump is not dipped with the flux; contacting the first bumps to the corresponding inner leads; proceeding with a reflow so that the first bumps are melted and connected to the corresponding inner leads, and the second bump is connected to the corresponding inner lead without being melted, to maintain a gap between the chip and the inner leads to prevent collapse of the first bumps.
摘要翻译：引线框封装的倒装芯片和制造方法包括提供具有多个内引线的引线框架; 提供具有活性表面的芯片; 在所述有源表面上形成多个第一凸块和至少一个第二凸块，所述第一凸块的材料与所述第二凸块相同，并且所述第二凸块的高度低于所述第一凸块; 将第一凸块的顶部浸入焊剂中，使得第二凸块不与焊剂一起浸入; 使所述第一凸起与相应的内引线接触; 继续进行回流，使得第一凸起熔化并连接到相应的内引线，并且第二凸起连接到相应的内引线而不熔化，以保持芯片和内引线之间的间隙，以防止第一个颠簸

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式