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1. 发明授权

US08228976B2 Dual-port input equalizer 失效
标题翻译：双端口输入均衡器
公开(公告)号：US08228976B2
公开(公告)日：2012-07-24
申请号：US12650566
申请日：2009-12-31
申请人： Chiao-Wei Hsiao , Shyr-Chyau Luo , Chien-Cheng Tu
发明人： Chiao-Wei Hsiao , Shyr-Chyau Luo , Chien-Cheng Tu
IPC分类号： H03K5/159
CPC分类号： H04L25/03133
摘要： A dual-port input equalizer includes a control unit for generating a first control signal and a second control signal according to a selection signal, a first equalizer for receiving a first and second differential voltage for equalization according to the first control signal and the second control signal, which the first equalizer includes a first transistor, a second transistor, an passive loading portion, and a first zero-point generation circuit, a second equalizer for receiving a third and fourth differential voltage for equalization according to the first control signal and the second control signal, which the second equalizer includes a third transistor and a fourth transistor, which the drain of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the passive loading portion, and the source of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the first zero-point generation circuit.
摘要翻译：双端口输入均衡器包括用于根据选择信号产生第一控制信号和第二控制信号的控制单元，用于根据第一控制信号和第二控制接收用于均衡的第一和第二差分电压的第一均衡器信号，第一均衡器包括第一晶体管，第二晶体管，无源负载部分和第一零点产生电路;第二均衡器，用于根据第一控制信号接收用于均衡的第三和第四差分电压，第二控制信号，其中第二均衡器包括第三晶体管和第四晶体管，第一晶体管，第二晶体管，第三晶体管和第四晶体管的漏极耦合到无源负载部分，第一晶体管的源极，第二晶体管，第三晶体管和第四晶体管耦合到第一零点发生电路。

2. 发明申请

US20110032977A1 Dual-Port Input Equalizer 失效
标题翻译：双端口输入均衡器
公开(公告)号：US20110032977A1
公开(公告)日：2011-02-10
申请号：US12650566
申请日：2009-12-31
申请人： Chiao-Wei Hsiao , Shyr-Chyau Luo , Chien-Cheng Tu
发明人： Chiao-Wei Hsiao , Shyr-Chyau Luo , Chien-Cheng Tu
IPC分类号： H03K5/159
CPC分类号： H04L25/03133
摘要： A dual-port input equalizer includes a control unit for generating a first control signal and a second control signal according to a selection signal, a first equalizer for receiving a first and second differential voltage for equalization according to the first control signal and the second control signal, which the first equalizer includes a first transistor, a second transistor, an passive loading portion, and a first zero-point generation circuit, a second equalizer for receiving a third and fourth differential voltage for equalization according to the first control signal and the second control signal, which the second equalizer includes a third transistor and a fourth transistor, which the drain of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the passive loading portion, and the source of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the first zero-point generation circuit.
摘要翻译：双端口输入均衡器包括用于根据选择信号产生第一控制信号和第二控制信号的控制单元，用于根据第一控制信号和第二控制接收用于均衡的第一和第二差分电压的第一均衡器信号，第一均衡器包括第一晶体管，第二晶体管，无源负载部分和第一零点产生电路;第二均衡器，用于接收根据第一控制信号的均衡的第三和第四差分电压，第二控制信号，其中第二均衡器包括第三晶体管和第四晶体管，第一晶体管，第二晶体管，第三晶体管和第四晶体管的漏极耦合到无源负载部分，第一晶体管的源极，第二晶体管，第三晶体管和第四晶体管耦合到第一零点发生电路。

3. 发明申请

US20100215130A1 Method and Related Device for Detecting Signals in a TMDS Transmission System 有权
标题翻译：用于检测TMDS传输系统中的信号的方法和相关设备
公开(公告)号：US20100215130A1
公开(公告)日：2010-08-26
申请号：US12551577
申请日：2009-09-01
申请人： Chiao-Wei Hsiao , Kuo-Chi Chen , Shyr-Chyau Luo
发明人： Chiao-Wei Hsiao , Kuo-Chi Chen , Shyr-Chyau Luo
IPC分类号： H04L27/06
CPC分类号： H04L25/0272 , G09G5/006 , G09G2370/12 , H04L25/0292
摘要： A method for detecting signals in a TMDS transmission system is disclosed. A channel of the TMDS system is established between a receiver and a transmitter. The method includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference.
摘要翻译：公开了一种在TMDS传输系统中检测信号的方法。在接收机和发射机之间建立TMDS系统的通道。该方法包括从信道分离接收机的负载，在信道的第一差分线路中提供第一参考电流，在信道的第二差分线路中提供第二参考电流，计算第一参考电流和第由所述发射机经由所述第一差分线提供的电流以获得第一电流差，计算所述第二参考电流与由所述发射机经由所述第二差分线提供的电流之间的差以获得第二电流差，并且确定所述发射机根据所述第一电流差和所述第二电流差。

4. 发明授权

US08509317B2 Method and related device for detecting signals in a TMDS transmission system 有权
标题翻译：用于检测TMDS传输系统中的信号的方法和相关设备
公开(公告)号：US08509317B2
公开(公告)日：2013-08-13
申请号：US12551577
申请日：2009-09-01
申请人： Chiao-Wei Hsiao , Kuo-Chi Chen , Shyr-Chyau Luo
发明人： Chiao-Wei Hsiao , Kuo-Chi Chen , Shyr-Chyau Luo
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , G09G5/006 , G09G2370/12 , H04L25/0292
摘要： A method for detecting signals in a TMDS transmission system having a channel established between a receiver and a transmitter includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference.
摘要翻译：一种在具有在接收机和发射机之间建立的信道的TMDS传输系统中检测信号的方法，包括：从所述信道分离接收机的负载，在所述信道的第一差分线路中提供第一参考电流，提供第二参考电流，所述通道的第二差分线，经由所述第一差分线计算所述第一参考电流和所述发射器提供的电流之间的差以获得第一电流差，计算所述第二参考电流与所述发射器提供的电流之间的差经由第二差动线路获得第二电流差，根据第一电流差和第二电流差确定发送器的运行状态。

5. 发明授权

US08120392B2 Frequency dividing circuit 有权
标题翻译：分频电路
公开(公告)号：US08120392B2
公开(公告)日：2012-02-21
申请号：US12614508
申请日：2009-11-09
申请人： Chiao-Wei Hsiao , Chung-Wei Lin
发明人： Chiao-Wei Hsiao , Chung-Wei Lin
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/54
摘要： A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.
摘要翻译：分频电路对N个输入时钟信号进行分频操作，以获得N个输出时钟信号，其中N是大于1的自然数。分频电路包括分频器和触发器。分频器根据N个输入时钟信号的第一输入时钟信号对初始信号进行采样，从而产生N个输出时钟信号的第一输出时钟信号。初始信号对应于第一输出时钟信号的反相信号。触发器对第一输出时钟信号进行采样，从而根据N个输入时钟信号的第二输入时钟信号产生N个输出时钟信号的第二输出时钟信号。

6. 发明申请

US20100259106A1 SWITCHING CONTROL METHOD CAPABLE OF CONTINUOUSLY PROVIDING POWER AND RELATED APPARATUS AND POWER SUPPLY SYSTEM 有权
标题翻译：可连续供电的切换控制方法及相关设备及电源系统
公开(公告)号：US20100259106A1
公开(公告)日：2010-10-14
申请号：US12489443
申请日：2009-06-23
申请人： Sih-Ting Wang , Chiao-Wei Hsiao , Chung-Wen Wu
发明人： Sih-Ting Wang , Chiao-Wei Hsiao , Chung-Wen Wu
IPC分类号： H02J4/00
CPC分类号： H02J9/061 , H02J2009/068 , Y10T307/50 , Y10T307/696
摘要： A switching control method capable of continuously providing power is utilized for a power supply system having a first power supply unit and a second power supply unit. The switching control method includes generating a first input signal and a second input signal; performing a logical operation process on the first input signal and the second input signal to generate a first control signal; delaying the second input signal for a delay time to generate a second control signal; controlling a coupling relationship between the first power supply unit and a load according to the first control signal; and controlling a coupling relationship between the second power supply unit and the load according to the second control signal.
摘要翻译：具有连续供电功能的切换控制方法被用于具有第一电源单元和第二电源单元的电源系统。切换控制方法包括：生成第一输入信号和第二输入信号; 对所述第一输入信号和所述第二输入信号执行逻辑运算处理，以产生第一控制信号; 将所述第二输入信号延迟延迟时间以产生第二控制信号; 根据第一控制信号控制第一电源单元和负载之间的耦合关系; 以及根据第二控制信号控制第二电源单元和负载之间的耦合关系。

7. 发明申请

US20070133729A1 Spread ratio fixing circuit and method for generating spread spectrum clock 审中-公开
标题翻译：扩频比固定电路和产生扩频时钟的方法
公开(公告)号：US20070133729A1
公开(公告)日：2007-06-14
申请号：US11365769
申请日：2006-02-28
申请人： Chiao-Wei Hsiao , Chun-Yi Huang
发明人： Chiao-Wei Hsiao , Chun-Yi Huang
IPC分类号： H03D3/24
CPC分类号： H03D13/004 , H03L7/0893 , H03L7/093
摘要： An apparatus for generating a spread spectrum clock with constant spread ratio includes a resistance-capacitance oscillator which is used for generating a first clock signal. In addition, the present invention further includes a spread spectrum charge pump circuit, a loop filter, and a voltage controlled oscillator (VCO). The spread spectrum charge pump circuit generates a spread spectrum current according to the first clock signal for changing/discharging the loop filter, so as to make the loop filter generate a control voltage. The VCO generates a control current and a spread spectrum clock signal according to the control voltage. The VCO feeds the control current back to the spread spectrum charge pump circuit to generate the spread spectrum current.
摘要翻译：用于产生具有恒定扩展比的扩频时钟的装置包括用于产生第一时钟信号的电阻电容振荡器。此外，本发明还包括扩频电荷泵电路，环路滤波器和压控振荡器（VCO）。扩频电荷泵电路根据用于改变/放电环路滤波器的第一时钟信号产生扩频电流，以使环路滤波器产生控制电压。 VCO根据控制电压产生控制电流和扩频时钟信号。 VCO将控制电流馈送到扩频电荷泵电路以产生扩频电流。

8. 发明授权

US08593013B2 Switching control method capable of continuously providing power and related apparatus and power supply system 有权
标题翻译：开关控制方法能够连续提供电源及相关设备及电源系统
公开(公告)号：US08593013B2
公开(公告)日：2013-11-26
申请号：US12489443
申请日：2009-06-23
申请人： Sih-Ting Wang , Chiao-Wei Hsiao , Chung-Wen Wu
发明人： Sih-Ting Wang , Chiao-Wei Hsiao , Chung-Wen Wu
IPC分类号： H02J4/00
CPC分类号： H02J9/061 , H02J2009/068 , Y10T307/50 , Y10T307/696
摘要： A switching control method capable of continuously providing power is utilized for a power supply system having a first power supply unit and a second power supply unit. The switching control method includes generating a first input signal and a second input signal; performing a logical operation process on the first input signal and the second input signal to generate a first control signal; delaying the second input signal for a delay time to generate a second control signal; controlling a coupling relationship between the first power supply unit and a load according to the first control signal; and controlling a coupling relationship between the second power supply unit and the load according to the second control signal.
摘要翻译：具有连续供电功能的切换控制方法被用于具有第一电源单元和第二电源单元的电源系统。切换控制方法包括：生成第一输入信号和第二输入信号; 对所述第一输入信号和所述第二输入信号执行逻辑运算处理，以产生第一控制信号; 将所述第二输入信号延迟延迟时间以产生第二控制信号; 根据第一控制信号控制第一电源单元和负载之间的耦合关系; 以及根据第二控制信号控制第二电源单元和负载之间的耦合关系。

9. 发明授权

US08373474B2 Delay lock loop and method for generating clock signal 有权
标题翻译：延迟锁定环路和产生时钟信号的方法
公开(公告)号：US08373474B2
公开(公告)日：2013-02-12
申请号：US13244621
申请日：2011-09-25
申请人： Chiao-Wei Hsiao , Sih-Ting Wang
发明人： Chiao-Wei Hsiao , Sih-Ting Wang
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0816 , H03L7/091
摘要： A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided.
摘要翻译：提供了包括电压控制延迟线（VCDL），相位频率检测环路（PFD loop）和相位限制环路的延迟锁定环路（DLL）。 VCDL根据DC电压信号生成输出时钟信号，其中VCDL将输入时钟信号延迟特定周期，以产生输出时钟信号。 PFD环路根据输入时钟信号和输出时钟信号的相位差产生直流电压信号，并由起始信号控制。相位限制环路将输出时钟信号的延迟限制在小于延迟时间，并产生启动信号以使能PFD环路。此外，还提供了时钟信号生成方法。

10. 发明申请

US20120194237A1 DELAY LOCK LOOP AND METHOD FOR GENERATING CLOCK SIGNAL 有权
标题翻译：延迟锁定环路和产生时钟信号的方法
公开(公告)号：US20120194237A1
公开(公告)日：2012-08-02
申请号：US13244621
申请日：2011-09-25
申请人： Chiao-Wei Hsiao , Sih-Ting Wang
发明人： Chiao-Wei Hsiao , Sih-Ting Wang
IPC分类号： H03L7/08
CPC分类号： H03L7/087 , H03L7/0816 , H03L7/091
摘要： A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided.
摘要翻译：提供了包括电压控制延迟线（VCDL），相位频率检测环路（PFD loop）和相位限制环路的延迟锁定环路（DLL）。 VCDL根据DC电压信号生成输出时钟信号，其中VCDL将输入时钟信号延迟特定周期，以产生输出时钟信号。 PFD环路根据输入时钟信号和输出时钟信号的相位差产生直流电压信号，并由起始信号控制。相位限制环路将输出时钟信号的延迟限制在小于延迟时间，并产生启动信号以使能PFD环路。此外，还提供了时钟信号生成方法。

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