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1. 发明申请

US20100197119A1 Resistor Random Access Memory Cell Device 有权
标题翻译：电阻随机存取存储单元装置
公开(公告)号：US20100197119A1
公开(公告)日：2010-08-05
申请号：US12755897
申请日：2010-04-07
申请人： Erh Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/20
CPC分类号： H01L45/122 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.
摘要翻译：存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件材料。因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

2. 发明授权

US07800094B2 Resistance memory with tungsten compound and manufacturing 有权
标题翻译：电阻记忆与钨化合物和制造
公开(公告)号：US07800094B2
公开(公告)日：2010-09-21
申请号：US11955137
申请日：2007-12-12
申请人： ChiaHua Ho , Erh Kun Lai
发明人： ChiaHua Ho , Erh Kun Lai
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , B82Y10/00 , G11C11/14 , G11C11/22 , G11C11/5685 , G11C13/0007 , G11C2213/32 , G11C2213/51 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.
摘要翻译：描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。本文描述的存储器件包括底部电极和底部电极上的存储元件。存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

3. 发明申请

US20080157053A1 Resistor Random Access Memory Cell Device 有权
标题翻译：电阻随机存取存储单元装置
公开(公告)号：US20080157053A1
公开(公告)日：2008-07-03
申请号：US11617542
申请日：2006-12-28
申请人： Erh Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L47/00
CPC分类号： H01L45/122 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.
摘要翻译：存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件材料。因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

4. 发明授权

US07605079B2 Manufacturing method for phase change RAM with electrode layer process 有权
标题翻译：具有电极层工艺的相变RAM的制造方法
公开(公告)号：US07605079B2
公开(公告)日：2009-10-20
申请号：US11382799
申请日：2006-05-11
申请人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
IPC分类号： H01L21/44
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used inter-layer conductors for metallization layers, in order to improve process scaling with shrinking critical dimensions for metallization layers. The electrode layer is made by forming a multi-layer dielectric layer on a substrate, etching the multi-layer dielectric layer to form vias for electrode members contacting circuitry below, forming insulating spacers on the vias, etching through a top layer in the multi-layer dielectric layer to form trenches between the insulating spacers for electrode members contacting circuitry above, filling the vias and trenches with a conductive material using the metallization process. Thin film bridges of memory material are formed over the electrode layer.
摘要翻译：一种相变存储器件的制造方法，包括形成电极层。使用导体填充技术在电极层中制造电极，该技术也用于金属化层的层间导体，以便通过金属化层的缩小临界尺寸改善工艺规模。电极层是通过在衬底上形成多层电介质层而形成的，蚀刻多层电介质层以形成接触下面电路的电极构件的通路，在通孔上形成绝缘隔离层，以在用于接触上述电路的电极部件的绝缘间隔物之间形成沟槽，用导电材料使用金属化工艺填充过孔和沟槽。存储材料的薄膜桥形成在电极层上。

5. 发明申请

US20090101883A1 Method for manufacturing a resistor random access memory with a self-aligned air gap insulator 有权
标题翻译：具有自对准气隙绝缘体的电阻随机存取存储器的制造方法
公开(公告)号：US20090101883A1
公开(公告)日：2009-04-23
申请号：US11977088
申请日：2007-10-23
申请人： Erh Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/28 , H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/148
摘要： A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.
摘要翻译：包括可编程电阻性存储器材料的存储器件与用于制造存储器件的方法一起被描述。本文公开的存储器件包括顶部和底部电极以及设置在顶部和底部电极之间的多层叠层。多层堆叠包括存储元件，其包括可编程电阻存储器材料并具有侧壁表面。气隙与侧壁表面相邻并且与存储元件自对准。

6. 发明授权

US08106376B2 Method for manufacturing a resistor random access memory with a self-aligned air gap insulator 有权
标题翻译：具有自对准气隙绝缘体的电阻随机存取存储器的制造方法
公开(公告)号：US08106376B2
公开(公告)日：2012-01-31
申请号：US11977088
申请日：2007-10-23
申请人： Erh Kun Lai , Kuang Yeu Hsieh , ChiaHua Ho
发明人： Erh Kun Lai , Kuang Yeu Hsieh , ChiaHua Ho
IPC分类号： H01L47/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/148
摘要： A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.
摘要翻译：包括可编程电阻性存储器材料的存储器件与用于制造存储器件的方法一起被描述。本文公开的存储器件包括顶部和底部电极以及设置在顶部和底部电极之间的多层叠层。多层堆叠包括存储元件，其包括可编程电阻存储器材料并具有侧壁表面。气隙与侧壁表面相邻并且与存储元件自对准。

7. 发明授权

US07595218B2 Programmable resistive RAM and manufacturing method 有权
标题翻译：可编程电阻RAM及制造方法
公开(公告)号：US07595218B2
公开(公告)日：2009-09-29
申请号：US11461103
申请日：2006-07-31
申请人： ChiaHua Ho , Erh Kun Lai , Kuang Yeu Hsieh
发明人： ChiaHua Ho , Erh Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , H01L27/24
摘要： Programmable resistive RAM cells have a resistance that depends on the size of the programmable resistive elements. Manufacturing methods and integrated circuits for programmable resistive elements with uniform resistance are disclosed that have a cross-section of reduced size compared to the cross-section of the interlayer contacts.
摘要翻译：可编程电阻RAM单元具有取决于可编程电阻元件的尺寸的电阻。公开了具有均匀电阻的可编程电阻元件的制造方法和集成电路，其具有与层间触点的横截面相比尺寸减小的横截面。

8. 发明申请

US20070158690A1 Programmable Resistive RAM and Manufacturing Method 有权
标题翻译：可编程电阻RAM和制造方法
公开(公告)号：US20070158690A1
公开(公告)日：2007-07-12
申请号：US11461103
申请日：2006-07-31
申请人： ChiaHua Ho , Erh Kun Lai , Kuang Yeu Hsieh
发明人： ChiaHua Ho , Erh Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/101 , H01L27/24
摘要： Programmable resistive RAM cells have a resistance that depends on the size of the programmable resistive elements. Manufacturing methods and integrated circuits for programmable resistive elements with uniform resistance are disclosed that have a cross-section of reduced size compared to the cross-section of the interlayer contacts.
摘要翻译：可编程电阻RAM单元具有取决于可编程电阻元件的尺寸的电阻。公开了具有均匀电阻的可编程电阻元件的制造方法和集成电路，其具有与层间触点的横截面相比尺寸减小的横截面。

9. 发明申请

US20070155172A1 Manufacturing Method for Phase Change RAM with Electrode Layer Process 有权
标题翻译：具有电极层工艺的相变RAM的制造方法
公开(公告)号：US20070155172A1
公开(公告)日：2007-07-05
申请号：US11382799
申请日：2006-05-11
申请人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chiahua Ho , Yi Chou Chen , Kuang Yeu Hsieh
IPC分类号： H01L21/44
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used inter-layer conductors for metallization layers, in order to improve process scaling with shrinking critical dimensions for metallization layers. The electrode layer is made by forming a multi-layer dielectric layer on a substrate, etching the multi-layer dielectric layer to form vias for electrode members contacting circuitry below, forming insulating spacers on the vias, etching through a top layer in the multi-layer dielectric layer to form trenches between the insulating spacers for electrode members contacting circuitry above, filling the vias and trenches with a conductive material using the metallization process. Thin film bridges of memory material are formed over the electrode layer.
摘要翻译：一种相变存储器件的制造方法，包括形成电极层。使用导体填充技术在电极层中制造电极，该技术也用于金属化层的层间导体，以便通过金属化层的缩小临界尺寸改善工艺规模。电极层是通过在衬底上形成多层电介质层而形成的，蚀刻多层电介质层以形成接触下面电路的电极构件的通路，在通孔上形成绝缘隔离层，以在用于接触上述电路的电极部件的绝缘间隔物之间形成沟槽，用导电材料使用金属化工艺填充过孔和沟槽。存储材料的薄膜桥形成在电极层上。

10. 发明申请

US20070278529A1 RESISTOR RANDOM ACCESS MEMORY CELL WITH L-SHAPED ELECTRODE 有权
标题翻译：电阻随机存取存储器与L形电极
公开(公告)号：US20070278529A1
公开(公告)日：2007-12-06
申请号：US11421036
申请日：2006-05-30
申请人： Erh Kun Lai , Chia Hua Ho , Kuang Yeu Hsieh
发明人： Erh Kun Lai , Chia Hua Ho , Kuang Yeu Hsieh
IPC分类号： H01L27/10 , H01L21/8234
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.
摘要翻译：描述适用于大规模集成电路的相变随机存取存储器PCRAM器件。示例性存储器件具有由侧壁支撑结构的侧壁上的第一电极层形成的管状第一电极。侧壁间隔绝缘部件由第一氧化物层形成，第二“L”形电极形成在绝缘部件上。电触头连接到第二电极的水平部分。记忆材料桥从第一电极的顶表面延伸到第二电极的顶表面，跨过侧壁间隔绝缘件的顶表面。

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