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1. 发明授权

US08468472B1 Computing device and method of checking wiring diagrams 失效
标题翻译：检查接线图的计算机和方法
公开(公告)号：US08468472B1
公开(公告)日：2013-06-18
申请号：US13456241
申请日：2012-04-26
申请人： Ya-Ling Huang , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Ya-Ling Huang , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： G06F50/17
CPC分类号： G06F17/5081 , G06F2217/82
摘要： In a computing device, computerized method, and a non-transitory storage medium, plug-in capacitors are selected from capacitors in a wiring diagram according pin information of the capacitors. A straight line is constructed for each of the plug-in capacitors according to size of holes where pins of the plug-in capacitor are to be inserted into. Paths of all transmission lines in the wiring diagram are obtained, and a determination of, whether any of the paths has at least one intersection point with at least one constructed straight line, is made. One or more paths, which have at least one intersection point with at least one constructed straight line, are recorded into a path list. The path list is then outputted using the computing device.
摘要翻译：在计算设备，计算机化方法和非暂时性存储介质中，根据电容器的引脚信息，在接线图中从电容器中选择插入式电容器。根据插入电容器的插脚孔的尺寸，为每个插入式电容器构建直线。获得接线图中的所有传输线的路径，并且确定是否有任何路径与至少一个构造的直线至少具有一个交点。具有至少一个与至少一个构造的直线的交点的一个或多个路径被记录到路径列表中。然后使用计算设备输出路径列表。

2. 发明授权

US08458645B2 Electronic device and method for checking layout of printed circuit board 失效
标题翻译：用于检查印刷电路板布局的电子装置和方法
公开(公告)号：US08458645B2
公开(公告)日：2013-06-04
申请号：US13407768
申请日：2012-02-29
申请人： Chia-Nan Pai , Shou-Kuo Hsu , Ya-Ling Huang
发明人： Chia-Nan Pai , Shou-Kuo Hsu , Ya-Ling Huang
IPC分类号： G06F17/50 , G06F15/04
CPC分类号： G06F17/5081
摘要： In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.
摘要翻译：在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择信号线。该方法搜索在PCB布局图中偏离直线时具有锐角的信号线。该方法进一步在PCB的布局图中定位搜索到的信号线的属性数据，并将所搜索的信号线的属性数据显示在电子设备的显示装置上。

3. 发明授权

US08438529B1 Computing device and method for checking signal transmission line 失效
标题翻译：检测信号传输线的计算装置及方法
公开(公告)号：US08438529B1
公开(公告)日：2013-05-07
申请号：US13585854
申请日：2012-08-15
申请人： Ya-Ling Huang , Ling-Ling Shen , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Ya-Ling Huang , Ling-Ling Shen , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-based method and a computing device for checking signal transmission lines of a printed circuit board (PCB) layout are provided. The computing device identifies differential pairs in a currently run PCB layout according to an information file for the currently run PCB layout, checks whether any signal transmission line is routed between switching vias of each differential pair according to the information file for the currently run PCB layout, and displays a routing error window to display information of each misrouted signal transmission line.
摘要翻译：提供了一种用于检查印刷电路板（PCB）布局的信号传输线的基于计算机的方法和计算装置。根据当前运行的PCB布局的信息文件，计算设备根据当前运行的PCB布局的信息文件识别当前运行的PCB布局中的差分对，根据当前运行的PCB布局的信息文件，检查每个差分对的切换通孔之间是否有任何信号传输线路由，并显示路由错误窗口以显示每条错误路由的信号传输线路的信息。

4. 发明授权

US08441327B2 Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：US08441327B2
公开(公告)日：2013-05-14
申请号：US12960321
申请日：2010-12-03
申请人： Hua-Li Zhou , Ming Wei , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Hua-Li Zhou , Ming Wei , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： H03H7/38
CPC分类号： H05K1/0245 , H05K2201/09727
摘要： A printed circuit board includes an insulation layer and a signal layer attached to the insulation layer. The signal layer includes a pair of differential transmission lines. Width W of each of the differential transmission lines is changed according to change of space S between the differential transmission lines, based on the following formula: W = C ⁢ ⁢ 1 × H × ( C ⁢ ⁢ 2 × H 0.8 ⁢ W 0 + T ) C ⁢ ⁢ 3 × ⅇ C ⁢ ⁢ 4 × S 0 H - 1 1 - C ⁢ ⁢ 3 × ⅇ C ⁢ ⁢ 4 × S H - 1.25 ⁢ T In above formula, C1=7.475, C2=5.98, C3=0.48, C4=−0.96, H is a thickness of the insulation layer, W0 is an original width of each of the differential transmission lines, and S0 is an original space between the differential transmission lines, and T is a thickness of each of the differential transmission lines.
摘要翻译：印刷电路板包括绝缘层和附着到绝缘层的信号层。信号层包括一对差动传输线。差分传输线路的宽度W根据以下公式根据差分传输线路之间的空间S的变化而变化：W = C⁢1×H×（Cé2×H 0.8W 0 + T）C uch 3×ⅇC ud 4×S 0 H-1 1 -C⁢3×ⅇC ud 4×SH-1.25T在上式中，C1 = 7.475，C2 = 5.98，C3 = 0.48，C4 = -0.96，H是绝缘层的厚度，W0是差分传输线的原始宽度，S0是差动传输线之间的原始空间，T是各个差分传输线的厚度差动传输线。

5. 发明授权

US08402423B2 System and method for verifying PCB layout 失效
标题翻译：验证PCB布局的系统和方法
公开(公告)号：US08402423B2
公开(公告)日：2013-03-19
申请号：US13244625
申请日：2011-09-25
申请人： Zheng Shan , Shi-Piao Luo , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Zheng Shan , Shi-Piao Luo , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077
摘要： In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.
摘要翻译：在使用计算装置验证印刷电路板（PCB）布局的方法中，从计算装置的存储装置获得PCB模拟文件，并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点（SVRN）。从PCB图像中选择要检查的SVRN，并搜索SVRN周围的所有信号线。该方法计算所选择的SVRN与所搜索的信号线之间的布局距离，并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。

6. 发明授权

US08247704B2 Motherboard interconnection device 有权
标题翻译：主板互连设备
公开(公告)号：US08247704B2
公开(公告)日：2012-08-21
申请号：US12503680
申请日：2009-07-15
申请人： Chia-Nan Pai , Han-Long Chen , Ning Li , Shou-Kuo Hsu
发明人： Chia-Nan Pai , Han-Long Chen , Ning Li , Shou-Kuo Hsu
IPC分类号： H05K1/18 , H05K3/30
CPC分类号： H05K1/0239 , H05K1/0245 , H05K1/0295 , H05K1/113 , H05K3/429 , H05K2201/044 , H05K2201/09254 , H05K2201/10015 , H05K2201/10545 , H05K2201/10636 , Y02P70/611 , Y10T29/4913
摘要： A motherboard interconnection device includes a top layer, a bottom layer, a first and a third electronic elements positioned on the top layer, and a second and a fourth electronic elements positioned on the bottom layer. A first end of the first electronic element on the top layer is connected to the first end of the second electronic element on the bottom layer with a first via hole, and the first end of the third electronic element on the top layer is connected to the first end of the fourth electronic element on the bottom layer with a second via hole. The second ends of the two electronic elements on the top layer are connected to a first part, and the second ends of the two electronic elements on the bottom layer are connected to a second part.
摘要翻译：母板互连装置包括顶层，底层，位于顶层上的第一和第三电子元件以及位于底层上的第二和第四电子元件。顶层上的第一电子元件的第一端通过第一通孔连接到底层上的第二电子元件的第一端，并且顶层上的第三电子元件的第一端连接到第四电子元件的第一端部具有第二通孔。顶层上的两个电子元件的第二端连接到第一部分，底层上的两个电子元件的第二端连接到第二部分。

7. 发明授权

US08194412B2 Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：US08194412B2
公开(公告)日：2012-06-05
申请号：US12647395
申请日：2009-12-25
申请人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： H05K1/18 , H05K1/16 , H05K7/00
CPC分类号： H05K1/0253 , H05K1/181 , H05K2201/09381 , H05K2201/0969 , H05K2201/10015 , H05K2201/10022 , H05K2201/10636 , Y02P70/611
摘要： A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8 ⁢ Wpad + 10 ⁢ T 0.8 ⁢ Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.
摘要翻译：印刷电路板包括信号平面和参考平面。信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。参考平面为通过无源元件和信号传输线传输的信号提供返回路径。在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8Wpad+ 10T 0.8Wtrace + T，其中Wpad是焊盘的宽度，Wtrace是传输线的宽度，T是焊盘的高度。

8. 发明授权

US08058557B2 Printed circuit board 失效
标题翻译：印刷电路板
公开(公告)号：US08058557B2
公开(公告)日：2011-11-15
申请号：US11957416
申请日：2007-12-15
申请人： Chien-Hung Liu , Shou-Kuo Hsu , Chia-Nan Pai
发明人： Chien-Hung Liu , Shou-Kuo Hsu , Chia-Nan Pai
IPC分类号： H05K1/00
CPC分类号： H05K1/0245 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672
摘要： An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.
摘要翻译：示例性PCB包括第一参考层，第一信号层，第二信号层和第三信号层，第一差分对以边缘耦合结构布置在第一信号层中，并参考第一参考层第一信号层和第二信号层之间的距离大于第一参考层和第一信号层之间的距离，第二差分对被布置在第二信号层中，第三信号层以广泛耦合结构。 PCB具有传输线高密度布局。

9. 发明授权

US08633401B2 Soldering pad 有权
标题翻译：焊盘
公开(公告)号：US08633401B2
公开(公告)日：2014-01-21
申请号：US13217626
申请日：2011-08-25
申请人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： H05K1/11
CPC分类号： H05K1/111 , H05K1/0242 , H05K1/025 , H05K2201/09736 , Y02P70/611
摘要： A pad includes a first mating section and a second mating section. The first mating section includes a first horizontal plane and a first inclined plane. The second mating section includes a second horizontal plane and a second inclined plane. The first mating section is a copper foil capable of being connected to a wire. The second mating section is made of insulating material. The first inclined plane and the second inclined plane are bonded together.
摘要翻译：垫包括第一配合部分和第二配合部分。第一配合部分包括第一水平面和第一倾斜平面。第二配合部分包括第二水平面和第二倾斜平面。第一配合部分是能够连接到电线的铜箔。第二配合部分由绝缘材料制成。第一倾斜平面和第二倾斜平面结合在一起。

10. 发明授权

US08510705B2 Computing device and method for checking via stub 失效
标题翻译：用于通过存根检查的计算设备和方法
公开(公告)号：US08510705B2
公开(公告)日：2013-08-13
申请号：US13327771
申请日：2011-12-16
申请人： Jia-Lu Ye , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Jia-Lu Ye , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length.
摘要翻译：提供了一种基于计算机的方法和用于检查印刷电路板（PCB）布局的通孔短截线的短截线长度的计算装置。计算装置显示检查接口，通过检查接口从当前运行的PCB布局中选择信号传输线，接收通过检查接口输入的参考短截线长度，并通过每个选定信号确定每个通孔短截线的实际短截线长度传输线连接。如果一个存根通孔的实际短截线长度小于或等于参考长度，则计算设备还确定一个通孔存根的设计满足设计标准，并且确定一个通孔存储体的设计不满足如果一个通过存根的实际存根长度大于参考短截线长度，则设计标准。

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