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1. 发明授权

US08041845B2 Method for detecting digital video interface off-line mode and associated receiver 有权
标题翻译：检测数字视频接口离线模式和相关接收机的方法
公开(公告)号：US08041845B2
公开(公告)日：2011-10-18
申请号：US12115239
申请日：2008-05-05
申请人： Chia-Ming Yang , Huimin Tsai
发明人： Chia-Ming Yang , Huimin Tsai
IPC分类号： G06F3/00 , H04N5/63
CPC分类号： G06F1/3203 , G06F1/3265 , Y02D10/153
摘要： A TMDS receiver includes a plurality of data channels, a clock channel, and an off-line mode detector. Each data channel receives a video signal and the clock channel receives a clock signal. Each data channel comprises a channel decoder for decoding the signals received by the corresponding receiving channel. The off-line mode detector detects an off-line mode detector, and then turns on a plurality of first data channels for a first predetermined period to determine an operation mode of video signal transmitted on said first data channels if the activity of the clock signal is valid. The off-line mode detector also activates a plurality of second data channels among the plurality of data channels according to the operation mode if the operation mode is determined as valid.
摘要翻译： TMDS接收机包括多个数据信道，时钟信道和离线模式检测器。每个数据通道接收视频信号，时钟信道接收时钟信号。每个数据信道包括用于对由相应接收信道接收的信号进行解码的信道解码器。离线模式检测器检测离线模式检测器，然后在第一预定周期内接通多个第一数据信道，以确定在所述第一数据信道上发送的视频信号的操作模式，如果时钟信号的活动已验证。如果操作模式被确定为有效，则离线模式检测器还根据操作模式激活多个数据通道中的多个第二数据通道。

2. 发明申请

US20080204561A1 METHOD FOR DETECTING DIGITAL VIDEO INTERFACE OFF-LINE MODE AND ASSOCIATED RECEIVER 有权
标题翻译：用于检测数字视频接口离线模式和相关接收器的方法
公开(公告)号：US20080204561A1
公开(公告)日：2008-08-28
申请号：US12115239
申请日：2008-05-05
申请人： Chia-Ming Yang , Huimin Tsai
发明人： Chia-Ming Yang , Huimin Tsai
IPC分类号： H04N17/00
CPC分类号： G06F1/3203 , G06F1/3265 , Y02D10/153
摘要： A TMDS receiver includes a plurality of data channels, a clock channel, and an off-line mode detector. Each data channel receives a video signal and the clock channel receives a clock signal. Each data channel comprises a channel decoder for decoding the signals received by the corresponding receiving channel. The off-line mode detector detects an off-line mode detector, and then turns on a plurality of first data channels for a first predetermined period to determine an operation mode of video signal transmitted on said first data channels if the activity of the clock signal is valid. The off-line mode detector also activates a plurality of second data channels among the plurality of data channels according to the operation mode if the operation mode is determined as valid.
摘要翻译： TMDS接收机包括多个数据信道，时钟信道和离线模式检测器。每个数据通道接收视频信号，时钟信道接收时钟信号。每个数据信道包括用于对由相应接收信道接收的信号进行解码的信道解码器。离线模式检测器检测离线模式检测器，然后在第一预定周期内接通多个第一数据信道，以确定在所述第一数据信道上发送的视频信号的操作模式，如果时钟信号的活动已验证。如果操作模式被确定为有效，则离线模式检测器还根据操作模式激活多个数据通道中的多个第二数据通道。

3. 发明申请

US20060190632A1 Method for detecting DVI off-line mode and associated DVI receiver 审中-公开
标题翻译：用于检测DVI离线模式和相关DVI接收机的方法
公开(公告)号：US20060190632A1
公开(公告)日：2006-08-24
申请号：US11055691
申请日：2005-02-11
申请人： Chia-Ming Yang , Huimin Tsai
发明人： Chia-Ming Yang , Huimin Tsai
IPC分类号： G06F3/00
CPC分类号： G06F1/3265 , G06F1/3203 , Y02D10/153
摘要： A method for detecting the DVI off-line mode and associated DVI receiver are provided. The DVI receiver comprises a plurality of receiving channels, a clock channel, and an off-line mode detector. Each receiving channel receives a video signal and the clock channel receives a clock signal. Each receiving channel comprises a channel decoder for decoding the signals received by the corresponding receiving channel. The off-line mode detector couples with the clock channel and the decoders. The off-line mode detector detects an activity of the clock signal to determine whether to turn on at least one receiving channel for a first predetermined period. The off-line mode detector comprises a mode detector, a clock detector, and a power down controller. The power down controller is coupled to the mode detector and the clock detector. The power down controller enables the mode detector to determine the operation mode of the video signal, and then the power down controller turns off all decoders and channels for a second predetermined period when the operation mode is determined as invalid. Preferably, the second predetermined period is much longer than the first predetermined period.
摘要翻译：提供了一种用于检测DVI离线模式和相关DVI接收机的方法。 DVI接收机包括多个接收信道，时钟信道和离线模式检测器。每个接收通道接收视频信号，时钟信道接收时钟信号。每个接收信道包括用于对由相应接收信道接收的信号进行解码的信道解码器。离线模式检测器与时钟通道和解码器耦合。离线模式检测器检测时钟信号的活动以确定是否在第一预定周期内接通至少一个接收信道。离线模式检测器包括模式检测器，时钟检测器和掉电控制器。断电控制器耦合到模式检测器和时钟检测器。断电控制器使得模式检测器能够确定视频信号的操作模式，然后当操作模式被确定为无效时，断电控制器将所有解码器和通道关闭第二预定周期。优选地，第二预定周期比第一预定周期长得多。

4. 发明授权

US06895542B2 Data recovery circuit and method and data receiving system using the same 有权
标题翻译：数据恢复电路及使用方法和数据接收系统
公开(公告)号：US06895542B2
公开(公告)日：2005-05-17
申请号：US10699649
申请日：2003-11-04
申请人： Sterling Smith , Huimin Tsai , Sheng-Yao Liu
发明人： Sterling Smith , Huimin Tsai , Sheng-Yao Liu
IPC分类号： G06F5/06 , H04L25/14 , H04L25/49 , H04N1/40 , G06F11/00
CPC分类号： H04L25/14 , G06F5/10 , H04L25/4908
摘要： A data recovery circuit for use in a data receiving system to recover an m-bit data stream from an n-bit data stream. The data recovery circuit comprises an n-bit data reconstruction circuit for selecting a data boundary in response to a boundary selection signal and producing a reconstructed n-bit data stream based on the boundary data, a FIFO buffer circuit for temporarily storing the reconstructed n-bit data stream and reading out the m-bit data stream, and a detection circuit for detecting whether the m-bit data stream from the FIFO buffer circuit conforms to a predetermined format and thereby producing a boundary selection signal for controlling the data boundary selection of the n-bit data reconstruction circuit.
摘要翻译：一种数据恢复电路，用于在数据接收系统中从n位数据流中恢复m位数据流。数据恢复电路包括：n比特数据重构电路，用于响应于边界选择信号选择数据边界，并且基于边界数据产生重建的n位数据流; FIFO缓冲电路，用于临时存储重建的n位数据，读出m位数据流;检测电路，用于检测来自FIFO缓冲电路的m位数据流是否符合预定格式，从而产生用于控制数据边界选择的边界选择信号 n位数据重建电路。

5. 发明申请

US20110080381A1 Portable Control Apparatus and Method Thereof 有权
标题翻译：便携式控制装置及其方法
公开(公告)号：US20110080381A1
公开(公告)日：2011-04-07
申请号：US12844413
申请日：2010-07-27
申请人： Huimin Tsai , Chi Kang Liu
发明人： Huimin Tsai , Chi Kang Liu
IPC分类号： G06F3/038 , H03J7/04
CPC分类号： H03J1/0008 , G06F1/08 , G09G2320/0693 , H03J7/04 , H03L7/06
摘要： A portable control apparatus includes a driver, a baseband controller, and a crystal oscillator. The driver includes an oscillating circuit that generates a feedback signal. The baseband controller coupled to the driver receives the feedback signal, and outputs a calibrating signal to the driver according to the feedback signal. The crystal oscillator coupled to the baseband controller generates an accurate output frequency for operating the baseband controller.
摘要翻译：便携式控制装置包括驱动器，基带控制器和晶体振荡器。驱动器包括产生反馈信号的振荡电路。耦合到驱动器的基带控制器接收反馈信号，并根据反馈信号向驱动器输出校准信号。耦合到基带控制器的晶体振荡器产生用于操作基带控制器的精确输出频率。

6. 发明授权

US07310397B2 Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions 有权
标题翻译：数据恢复电路，相位检测电路及相位条件检测与校正方法
公开(公告)号：US07310397B2
公开(公告)日：2007-12-18
申请号：US10698623
申请日：2003-11-03
申请人： Sterling Smith , Sheng-Yao Liu , Huimin Tsai
发明人： Sterling Smith , Sheng-Yao Liu , Huimin Tsai
IPC分类号： H04L7/00
CPC分类号： H04L7/0331
摘要： In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock pulses is used for sampling approximately the transition portions between every two adjacent data bits in the incoming data stream to produce a second sampled data stream. By detecting the resemblance of each bit in the second sampled data stream to the corresponding two adjacent bits in the first sampled data stream, a phase detection and correction circuit determines an early condition or a late condition for the phases of the sampling clocks and produces a signal to correct the phases of the sampling clocks by shifting the phases backwards or forwards. According to the invention, sampling clocks with lower frequencies can be used for sampling, and the phase error can be corrected to obtain the correct data recovery.
摘要翻译：在本发明的数据恢复电路中，第一组采样时钟脉冲被用于对输入数据流中的数据位的大部分中心部分采样以产生第一采样数据流，而第二组采样时钟脉冲是用于对输入数据流中每两个相邻数据位之间的过渡部分进行近似采样，以产生第二采样数据流。通过检测第二采样数据流中的每一比特相对于第一采样数据流中相应的两个相邻比特，相位检测和校正电路确定采样时钟的相位的早期状态或后期状态，并产生一个信号通过向后或向后移动相位来校正采样时钟的相位。根据本发明，可以使用具有较低频率的采样时钟进行采样，并且可以校正相位误差以获得正确的数据恢复。

7. 发明授权

US09093985B2 Portable control apparatus and method thereof for calibrating an oscillating circuit 有权
标题翻译：用于校准振荡电路的便携式控制装置及其方法
公开(公告)号：US09093985B2
公开(公告)日：2015-07-28
申请号：US12844413
申请日：2010-07-27
申请人： Huimin Tsai , Chi Kang Liu
发明人： Huimin Tsai , Chi Kang Liu
IPC分类号： H03J1/00 , G06F1/08 , H03J7/04 , H03L7/06
CPC分类号： H03J1/0008 , G06F1/08 , G09G2320/0693 , H03J7/04 , H03L7/06
摘要： A portable control apparatus includes a driver, a baseband controller, and a crystal oscillator. The driver includes an oscillating circuit that generates a feedback signal. The baseband controller coupled to the driver receives the feedback signal, and outputs a calibrating signal to the driver according to the feedback signal. The crystal oscillator coupled to the baseband controller generates an accurate output frequency for operating the baseband controller.
摘要翻译：便携式控制装置包括驱动器，基带控制器和晶体振荡器。驱动器包括产生反馈信号的振荡电路。耦合到驱动器的基带控制器接收反馈信号，并根据反馈信号向驱动器输出校准信号。耦合到基带控制器的晶体振荡器产生用于操作基带控制器的精确输出频率。

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