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1. 发明授权

US07427886B2 Clock generating method and circuit thereof 有权
标题翻译：时钟产生方法及其电路
公开(公告)号：US07427886B2
公开(公告)日：2008-09-23
申请号：US11161131
申请日：2005-07-25
申请人： Chia-Jung Yang
发明人： Chia-Jung Yang
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock generating method and circuit are provided. The circuit includes a basic clock unit, a plurality of subclock units, which are connected in parallel or in series, and a plurality of special control units (SCU). The basic clock unit provides a basic clock signal and each of the clock units provides a corresponding clock signal. Each of the special control units are disposed between two adjacent clock units to delay the clock signal generated by the clock unit connected to the output terminal of the special control units.
摘要翻译：提供时钟产生方法和电路。该电路包括并联或串联连接的基本时钟单元，多个副时钟单元以及多个特殊控制单元（SCU）。基本时钟单元提供基本时钟信号，并且每个时钟单元提供相应的时钟信号。每个特殊控制单元设置在两个相邻的时钟单元之间，以延迟由连接到特殊控制单元的输出端子的时钟单元产生的时钟信号。

2. 发明申请

US20080192030A1 Serial Data Transmission Method and Related Apparatus for Display Device 审中-公开
标题翻译：用于显示设备的串行数据传输方法和相关设备
公开(公告)号：US20080192030A1
公开(公告)日：2008-08-14
申请号：US11776551
申请日：2007-07-11
申请人： Chia-Jung Yang , Che-Li Lin
发明人： Chia-Jung Yang , Che-Li Lin
IPC分类号： G06F3/038
CPC分类号： G09G5/003
摘要： In order to mitigate signal reflections in a transmission interface of a display device, the present invention provides a serial transmission method for embedding data and non-data signals into transmission lines for a display device. The serial transmission method includes: obtaining a plurality of data transmission modes of the display device; defining a plurality of current patterns by a plurality of current intensities and a plurality of current directions according to the plurality of data transmission modes, each current pattern corresponding to one of the plurality of data transmission modes; and outputting one of the plurality of current patterns to an electronic device of the display device via a plurality of transmission lines according to a present data transmission mode.
摘要翻译：为了减轻显示装置的传输接口中的信号反射，本发明提供了一种用于将数据和非数据信号嵌入到显示装置的传输线中的串行传输方法。串行传输方法包括：获得显示设备的多个数据传输模式; 根据所述多个数据传输模式，通过多个电流强度和多个电流方向来定义多个当前图案，每个当前图案对应于所述多个数据传输模式之一; 并且根据本数据传输模式经由多条传输线路将多个当前图案中的一个输出到显示设备的电子设备。

3. 发明授权

US08786532B2 Pixel structure and forming method and driving method thereof 有权
标题翻译：像素结构及其形成方法及其驱动方法
公开(公告)号：US08786532B2
公开(公告)日：2014-07-22
申请号：US13495600
申请日：2012-06-13
申请人： Jenn-Jia Su , Ming-Feng Tien , Chia-Jung Yang , Ting-Jui Chang , Po-Lun Chen
发明人： Jenn-Jia Su , Ming-Feng Tien , Chia-Jung Yang , Ting-Jui Chang , Po-Lun Chen
IPC分类号： G09G3/36 , G02F1/1343
CPC分类号： G09G3/3648 , G02F2001/134345 , G02F2001/134354 , G09G2300/043 , G09G2300/0447 , G09G2300/0814 , G09G2310/06
摘要： A method for driving a pixel electrode disposed on a first substrate operates by providing a voltage corresponding to a displaying data to the pixel electrode and a control electrode, such that the pixel electrode and the control electrode are at a floating connection state; providing a first coupling voltage to a coupling electrode; and coupling a variation of a first coupling voltage to the control electrode via at least one coupling capacitor, such that an absolute value of a voltage difference between the control electrode and a common electrode substantially greater than an absolute value of a voltage difference between the pixel electrode and the common electrode, wherein the common electrode is disposed on a second substrate and the second substrate is corresponding to the first substrate.
摘要翻译：用于驱动设置在第一基板上的像素电极的方法通过向像素电极和控制电极提供与显示数据相对应的电压来操作，使得像素电极和控制电极处于浮动连接状态; 向耦合电极提供第一耦合电压; 并且经由至少一个耦合电容器将第一耦合电压的变化耦合到控制电极，使得控制电极和公共电极之间的电压差的绝对值基本上大于像素之间的电压差的绝对值电极和公共电极，其中所述公共电极设置在第二基板上，并且所述第二基板对应于所述第一基板。

4. 发明授权

US07834969B2 Multi-domain vertical alignment liquid crystal display panel 有权
标题翻译：多域垂直排列液晶显示面板
公开(公告)号：US07834969B2
公开(公告)日：2010-11-16
申请号：US11560852
申请日：2006-11-17
申请人： Chia-Jung Yang , Jenn-Jia Su , Chieh-Ting Chen , Ting-Jui Chang
发明人： Chia-Jung Yang , Jenn-Jia Su , Chieh-Ting Chen , Ting-Jui Chang
IPC分类号： G02F1/1337
CPC分类号： G02F1/1393 , G02F1/133707
摘要： A multi-domain vertical alignment (MVA) liquid crystal display panel includes an array substrate, a color filter (CF) substrate arranged in parallel to the array substrate, a plurality of bump patterns disposed on the CF substrate, and a plurality of transparent electrode patterns disposed on the array substrate. Each bump pattern includes a main bump corresponding to a pixel region, and at least one bump wing corresponding to a scan line or a data line. Each main bump includes a first protrusion connected to a side of the main bump. Each transparent electrode pattern includes a main slit. The transparent electrode pattern further includes a plurality of fine slits disposed in an inner side and in an outer side of the main slit. The fine slits disposed in the outer side of the main slit near the data line have different lengths.
摘要翻译：多域垂直取向（MVA）液晶显示面板包括阵列基板，与阵列基板平行布置的滤色器（CF）基板，设置在CF基板上的多个凸点图案，以及多个透明电极图案设置在阵列基板上。每个凸起图案包括对应于像素区域的主凸起以及对应于扫描线或数据线的至少一个凸块。每个主凸块包括连接到主凸起侧的第一突起。每个透明电极图案包括主狭缝。透明电极图案还包括设置在主狭缝的内侧和外侧的多个细缝。配置在数据线附近的主狭缝的外侧的细狭缝具有不同的长度。

5. 发明申请

US20120268443A1 Pixel Structure and Forming Method and Driving Method Thereof 有权
标题翻译：像素结构及其形成方法及其驱动方法
公开(公告)号：US20120268443A1
公开(公告)日：2012-10-25
申请号：US13495600
申请日：2012-06-13
申请人： Jenn-Jia Su , Ming-Feng Tien , Chia-Jung Yang , Ting-Jui Chang , Po-Lun Chen
发明人： Jenn-Jia Su , Ming-Feng Tien , Chia-Jung Yang , Ting-Jui Chang , Po-Lun Chen
IPC分类号： G09G3/36 , G06F3/038
CPC分类号： G09G3/3648 , G02F2001/134345 , G02F2001/134354 , G09G2300/043 , G09G2300/0447 , G09G2300/0814 , G09G2310/06
摘要： A method for driving a pixel electrode disposed on a first substrate operates by providing a voltage corresponding to a displaying data to the pixel electrode and a control electrode, such that the pixel electrode and the control electrode are at a floating connection state; providing a first coupling voltage to a coupling electrode; and coupling a variation of a first coupling voltage to the control electrode via at least one coupling capacitor, such that an absolute value of a voltage difference between the control electrode and a common electrode substantially greater than an absolute value of a voltage difference between the pixel electrode and the common electrode, wherein the common electrode is disposed on a second substrate and the second substrate is corresponding to the first substrate.
摘要翻译：用于驱动设置在第一基板上的像素电极的方法通过向像素电极和控制电极提供与显示数据相对应的电压来操作，使得像素电极和控制电极处于浮动连接状态; 向耦合电极提供第一耦合电压; 并且经由至少一个耦合电容器将第一耦合电压的变化耦合到控制电极，使得控制电极和公共电极之间的电压差的绝对值基本上大于像素之间的电压差的绝对值电极和公共电极，其中所述公共电极设置在第二基板上，并且所述第二基板对应于所述第一基板。

6. 发明授权

US08223100B2 Pixel structure and forming method and driving method thereof 有权
标题翻译：像素结构及其形成方法及其驱动方法
公开(公告)号：US08223100B2
公开(公告)日：2012-07-17
申请号：US12203291
申请日：2008-09-03
申请人： Jenn-Jia Su , Ming-Feng Tien , Chia-Jung Yang , Ting-Jui Chang , Po-Lun Chen
发明人： Jenn-Jia Su , Ming-Feng Tien , Chia-Jung Yang , Ting-Jui Chang , Po-Lun Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G02F2001/134345 , G02F2001/134354 , G09G2300/043 , G09G2300/0447 , G09G2300/0814 , G09G2310/06
摘要： A pixel structure, disposed on a first substrate, and electrically coupled to at least one scan line and at least one data line is provided. The pixel structure includes a first switch device, a second switch device, at least one pixel electrode, at least one control electrode, and at least one coupling electrode. The first switch device is electrically coupled to the scan line and the data line. The second switch device is electrically coupled to the scan line and the data line. The pixel electrode is electrically coupled to the second switch device. The control electrode is electrically coupled to the first switch element. The coupling electrode is disposed under the control electrode.
摘要翻译：提供了一种设置在第一基板上并且电耦合到至少一条扫描线和至少一条数据线的像素结构。像素结构包括第一开关器件，第二开关器件，至少一个像素电极，至少一个控制电极和至少一个耦合电极。第一开关器件电耦合到扫描线和数据线。第二开关器件电耦合到扫描线和数据线。像素电极电耦合到第二开关装置。控制电极电耦合到第一开关元件。耦合电极设置在控制电极下方。

7. 发明申请

US20060250173A1 CLOCK GENERATING METHOD AND CIRCUIT THEREOF 有权
标题翻译：时钟产生方法及其电路
公开(公告)号：US20060250173A1
公开(公告)日：2006-11-09
申请号：US11161131
申请日：2005-07-25
申请人： Chia-Jung Yang
发明人： Chia-Jung Yang
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock generating method and circuit are provided. The circuit includes a basic clock unit, a plurality of subclock units, which are connected in parallel or in series, and a plurality of special control units (SCU). The basic clock unit provides a basic clock signal and each of the clock units provides a corresponding clock signal. Each of the special control units are disposed between two adjacent clock units to delay the clock signal generated by the clock unit connected to the output terminal of the special control units.
摘要翻译：提供时钟产生方法和电路。该电路包括并联或串联连接的基本时钟单元，多个副时钟单元以及多个特殊控制单元（SCU）。基本时钟单元提供基本时钟信号，并且每个时钟单元提供相应的时钟信号。每个特殊控制单元设置在两个相邻的时钟单元之间，以延迟由连接到特殊控制单元的输出端子的时钟单元产生的时钟信号。

8. 发明授权

US07923957B2 Control system and method for motor drivers 有权
标题翻译：电机驱动器的控制系统和方法
公开(公告)号：US07923957B2
公开(公告)日：2011-04-12
申请号：US12252364
申请日：2008-10-16
申请人： Chia-Jung Yang , Fei-Hsu Chen
发明人： Chia-Jung Yang , Fei-Hsu Chen
IPC分类号： G05B19/404
CPC分类号： H02P1/56 , G05B19/404 , G05B2219/31458 , G05B2219/41414
摘要： A control method for motor driver includes: outputting a first signal from the controller to the first motor driver; making the first timer start to count for a first time; returning a first feedback signal from the first motor driver to the controller; dividing a value of a first count time of the first timer by two to get a value of a first delay time, wherein the first delay time is defined as the time of transmitting signals from the controller to the first motor driver; adding the value of the first delay time to the value of the first count time of the first timer to get a first sum; and transferring the first sum to the second timer to replace a value of a count time of the second timer.
摘要翻译：电动机驱动器的控制方法包括：从控制器向第一电动机驱动器输出第一信号; 使第一个定时器第一次开始计数; 将第一反馈信号从第一马达驱动器返回到控制器; 将第一定时器的第一计数时间的值除以2以获得第一延迟时间的值，其中第一延迟时间被定义为从控制器向第一马达驱动器发送信号的时间; 将第一延迟时间的值添加到第一计时器的第一计数时间的值以获得第一和; 以及将所述第一和传送到所述第二定时器以替换所述第二定时器的计数时间的值。

9. 发明授权

US07493485B2 Structure of embedded memory unit with loader and system structure and operation method for the embedded memory apparatus 有权
标题翻译：具有加载器的嵌入式存储单元的结构和嵌入式存储设备的系统结构和操作方法
公开(公告)号：US07493485B2
公开(公告)日：2009-02-17
申请号：US11160823
申请日：2005-07-12
申请人： Yung-Lung Chen , Chia-Jung Yang
发明人： Yung-Lung Chen , Chia-Jung Yang
IPC分类号： G06F15/177 , G06F9/445 , G06F9/24
CPC分类号： G06F9/4401
摘要： A structure of embedded memory unit with loader comprises a main memory area and an information area as a part of the main memory area. A plurality of loader-program parts is dispersedly stored in different addresses of the main memory area, wherein the loader-program parts are combined to form a complete loader. A loader mapping area is used to store the loader-program during the boot stage. When the boot sequence starts, the original information stored in the loader mapping area is temporarily backup to a temporary space; and the released space is used to store the loader-program. After the boot sequence is completed, the original information is moved back to the original location.
摘要翻译：具有加载器的嵌入式存储器单元的结构包括作为主存储区域的一部分的主存储区域和信息区域。多个加载程序部件分散地存储在主存储区域的不同地址中，其中加载程序部件被组合以形成完整的加载程序。加载程序映射区域用于在引导阶段存储加载程序程序。当引导序列开始时，存储在加载器映射区域中的原始信息暂时备份到临时空间; 并且释放的空间用于存储加载程序程序。引导顺序完成后，将原始信息移回原始位置。

10. 发明申请

US20080024706A1 MULTI-DOMAIN VERTICAL ALIGNMENT LIQUID CRYSTAL DISPLAY PANEL 有权
标题翻译：多域垂直对准液晶显示面板
公开(公告)号：US20080024706A1
公开(公告)日：2008-01-31
申请号：US11560852
申请日：2006-11-17
申请人： Chia-Jung Yang , Jenn-Jia Su , Chieh-Ting Chen , Ting-Jui Chang
发明人： Chia-Jung Yang , Jenn-Jia Su , Chieh-Ting Chen , Ting-Jui Chang
IPC分类号： G02F1/1337
CPC分类号： G02F1/1393 , G02F1/133707
摘要： A multi-domain vertical alignment (MVA) liquid crystal display panel includes an array substrate, a color filter (CF) substrate arranged in parallel to the array substrate, a plurality of bump patterns disposed on the CF substrate, and a plurality of transparent electrode patterns disposed on the array substrate. Each bump pattern includes a main bump corresponding to a pixel region, and at least one bump wing corresponding to a scan line or a data line. Each main bump includes a first protrusion connected to a side of the main bump. Each transparent electrode pattern includes a main slit. The transparent electrode pattern further includes a plurality of fine slits disposed in an inner side and in an outer side of the main slit. The fine slits disposed in the outer side of the main slit near the data line have different lengths.
摘要翻译：多域垂直取向（MVA）液晶显示面板包括阵列基板，与阵列基板平行布置的滤色器（CF）基板，设置在CF基板上的多个凸点图案，以及多个透明电极图案设置在阵列基板上。每个凸起图案包括对应于像素区域的主凸起以及对应于扫描线或数据线的至少一个凸块。每个主凸块包括连接到主凸起侧的第一突起。每个透明电极图案包括主狭缝。透明电极图案还包括设置在主狭缝的内侧和外侧的多个细缝。配置在数据线附近的主狭缝的外侧的细狭缝具有不同的长度。

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