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1. 发明授权

US06271096B1 Method and device for improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅闸门上提高耐化学性的方法和装置
公开(公告)号：US06271096B1
公开(公告)日：2001-08-07
申请号：US09458537
申请日：1999-12-09
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

2. 发明授权

US06777760B1 Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates 有权
标题翻译：具有凹陷的薄而厚的间隔物的装置，用于改善多晶硅栅极上的耐着雾性
公开(公告)号：US06777760B1
公开(公告)日：2004-08-17
申请号：US09477870
申请日：2000-01-05
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J Keating , Alan Myers
IPC分类号： H01L2994
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

3. 发明授权

US06506652B2 Method of recessing spacers to improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅栅极上使间隔物凹陷的方法提高了耐剥落性
公开(公告)号：US06506652B2
公开(公告)日：2003-01-14
申请号：US09458357
申请日：1999-12-09
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

4. 发明授权

US06188117B1 Method and device for improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅闸门上提高耐化学性的方法和装置
公开(公告)号：US06188117B1
公开(公告)日：2001-02-13
申请号：US09276477
申请日：1999-03-25
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L3300
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved polycide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下多晶硅栅极中提高多晶硅栅极电阻的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

5. 发明授权

US06521964B1 Device having spacers for improved salicide resistance on polysilicon gates 有权
标题翻译：具有用于在多晶硅栅极上提高自杀化剂电阻的间隔物的装置
公开(公告)号：US06521964B1
公开(公告)日：2003-02-18
申请号：US09386495
申请日：1999-08-30
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L2976
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

6. 发明授权

US06251762B1 Method and device for improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅闸门上提高耐化学性的方法和装置
公开(公告)号：US06251762B1
公开(公告)日：2001-06-26
申请号：US09458572
申请日：1999-12-09
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L213205
CPC分类号： H01L29/665
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;M. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20微米以下改善多晶硅闸门耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

7. 发明授权

US07211872B2 Device having recessed spacers for improved salicide resistance on polysilicon gates 有权
标题翻译：具有用于在多晶硅栅极上提高自杀化剂电阻的凹进间隔物的装置
公开(公告)号：US07211872B2
公开(公告)日：2007-05-01
申请号：US09477764
申请日：2000-01-04
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack within inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔件内部间隔堆叠和薄的外部间隔件。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

8. 发明授权

US06593633B2 Method and device for improved salicide resistance on polysilicon gates 有权
标题翻译：具有薄间隔物的装置，以改善多晶硅栅极上的耐着雾性
公开(公告)号：US06593633B2
公开(公告)日：2003-07-15
申请号：US09477869
申请日：2000-01-05
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L2976
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

9. 发明授权

US06509618B2 Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates 失效
标题翻译：器件具有薄的第一间隔物和部分凹入的厚的第二间隔物，用于在多晶硅栅极上提高改善的耐着
公开(公告)号：US06509618B2
公开(公告)日：2003-01-21
申请号：US09476920
申请日：2000-01-04
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L2976
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

10. 发明授权

US06268254B1 Method and device for improved salicide resistance on polysilicon gates 有权
公开(公告)号：US06268254B1
公开(公告)日：2001-07-31
申请号：US09458538
申请日：1999-12-09
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

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