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1. 发明授权

US08799730B2 Semiconductor devices and semiconductor packages 有权
标题翻译：半导体器件和半导体封装
公开(公告)号：US08799730B2
公开(公告)日：2014-08-05
申请号：US13453447
申请日：2012-04-23
申请人： Chi-sung Oh , Jung-sik Kim , Ho-cheol Lee , Jung-bae Lee
发明人： Chi-sung Oh , Jung-sik Kim , Ho-cheol Lee , Jung-bae Lee
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/40 , G01R31/3187
CPC分类号： G01R31/318555 , G01R31/318538 , G01R31/318597 , G01R31/3187 , H01L22/32 , H01L23/481 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13541 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/81193 , H01L2924/12042 , H01L2924/15192 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2924/206
摘要： Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.
摘要翻译：半导体器件被配置为测试包括一个或多个微凸块的微凸块和边界扫描测试块的连接性，用于通过扫描输入到微凸块的数据并输出扫描数据来测试微凸块的连接性。半导体器件可以包括第一芯片，其包括焊球和与各个焊球电耦合的至少一个或多个开关，以及堆叠在第一芯片的顶部上并与直流存取模式的开关电耦合的第二芯片，包括微从焊球传出的输入/输出信号的凸起。

2. 发明申请

US20130016574A1 SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REFRESH CHARACTERISTICS 有权
标题翻译：具有改进的刷新特性的半导体存储器件
公开(公告)号：US20130016574A1
公开(公告)日：2013-01-17
申请号：US13548484
申请日：2012-07-13
申请人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
发明人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
IPC分类号： G11C29/08 , G11C7/00
CPC分类号： G11C29/50016 , G11C5/04 , G11C11/40 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4061 , G11C2211/4065
摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.
摘要翻译：具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

3. 发明授权

US09036439B2 Semiconductor memory device having improved refresh characteristics 有权
标题翻译：具有改善的刷新特性的半导体存储器件
公开(公告)号：US09036439B2
公开(公告)日：2015-05-19
申请号：US13548484
申请日：2012-07-13
申请人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
发明人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
IPC分类号： G11C29/08 , G11C7/00 , G11C29/50 , G11C11/406 , G11C5/04 , G11C11/40
CPC分类号： G11C29/50016 , G11C5/04 , G11C11/40 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4061 , G11C2211/4065
摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.
摘要翻译：具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

4. 发明授权

US08446988B2 System and method for selectively performing single-ended and differential signaling 有权
标题翻译：用于选择性地执行单端和差分信号的系统和方法
公开(公告)号：US08446988B2
公开(公告)日：2013-05-21
申请号：US13280456
申请日：2011-10-25
申请人： Hoe-ju Chung , Jung-bae Lee
发明人： Hoe-ju Chung , Jung-bae Lee
IPC分类号： H04L27/06
CPC分类号： H04L25/0264 , H04L25/0272
摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.
摘要翻译：在通信系统中，使用单端或差分信令有选择地发送数据。相对于具有不同相对相位的多个时钟信号发送数据。当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

5. 发明授权

US07957217B2 Method of controlling internal voltage and multi-chip package memory prepared using the same 有权
标题翻译：控制内部电压的方法和使用其制备的多芯片封装存储器
公开(公告)号：US07957217B2
公开(公告)日：2011-06-07
申请号：US12266716
申请日：2008-11-07
申请人： Moon-sook Park , Hoe-ju Chung , Jung-bae Lee
发明人： Moon-sook Park , Hoe-ju Chung , Jung-bae Lee
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C5/04
摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.
摘要翻译：本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

6. 发明授权

US07948272B2 Input buffer for detecting an input signal 失效
标题翻译：用于检测输入信号的输入缓冲器
公开(公告)号：US07948272B2
公开(公告)日：2011-05-24
申请号：US10990412
申请日：2004-11-18
申请人： Dong-jin Lee , Jung-bae Lee , Kyu-hyoun Kim
发明人： Dong-jin Lee , Jung-bae Lee , Kyu-hyoun Kim
IPC分类号： H03K5/22
CPC分类号： H03K19/003
摘要： An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.
摘要翻译：输入缓冲器，用于检测输入信号。输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。第二缓冲器可以将输出节点维持在第一级。第二缓冲器可以包括输出控制部分和电平控制单元。输出控制部分可以接收输入信号并产生第二电平的电平输出信号。当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截当参考电压信号的电压电平等于预定电压电平时，控制信号。

7. 发明申请

US20080205113A1 Inter-transmission multi memory chip, system including the same and associated method 有权
标题翻译：传输多内存芯片，系统包括相同和相关的方法
公开(公告)号：US20080205113A1
公开(公告)日：2008-08-28
申请号：US12071745
申请日：2008-02-26
申请人： UK-song Kang , Jung-bae Lee
发明人： UK-song Kang , Jung-bae Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C5/04
摘要： A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.
摘要翻译：堆叠在多核CPU上的多存储器芯片包括多个存储器，每个存储器对应于CPU核心中的CPU核心，并且被配置为直接在多存储器芯片的其他存储器之间传输数据。

8. 发明授权

US07236012B2 Data output driver that controls slew rate of output signal according to bit organization 失效
标题翻译：数据输出驱动器，根据位组织控制输出信号的转换速率
公开(公告)号：US07236012B2
公开(公告)日：2007-06-26
申请号：US10970016
申请日：2004-10-22
申请人： Geun-hee Cho , Jung-bae Lee
发明人： Geun-hee Cho , Jung-bae Lee
IPC分类号： H03K19/0175
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.
摘要翻译：半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

9. 发明申请

US20050240718A1 Memory system and data channel initialization method for memory system 失效
标题翻译：内存系统和数据通道初始化方法
公开(公告)号：US20050240718A1
公开(公告)日：2005-10-27
申请号：US11071586
申请日：2005-03-04
申请人： Hoe-ju Chung , Jung-bae Lee
发明人： Hoe-ju Chung , Jung-bae Lee
IPC分类号： G11C7/10 , G06F12/00 , G06F12/14 , G06F12/16 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4243
摘要： Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.
摘要翻译：提供了一种可以高速初始化数据信道的存储器系统和方法，而不需要增加半导体存储器件中的引脚数量，并且不需要电路来执行初始化。存储器系统包括配备有多个半导体存储器件的存储器模块; 控制半导体存储器件的存储器控制器; 以及连接在所述多个半导体存储器件和所述存储器控制器之间的数据通道和命令/地址通道，其中所述多个半导体存储器件的读取延迟和写入延迟由所述存储器控制器控制。

10. 发明授权

US06804163B2 Semiconductor memory device for reducing chip size 有权
标题翻译：用于减小芯片尺寸的半导体存储器件
公开(公告)号：US06804163B2
公开(公告)日：2004-10-12
申请号：US10305986
申请日：2002-11-29
申请人： Yun-sang Lee , Jung-bae Lee
发明人： Yun-sang Lee , Jung-bae Lee
IPC分类号： G11C800
CPC分类号： G11C7/12 , G11C5/025 , G11C7/06 , G11C7/10
摘要： A semiconductor memory device that minimizes chip area is provided. The semiconductor memory device includes local input/output (I/O) lines, global I/O lines, and a memory core that is coupled between a bit line and a complementary bit line. The memory core includes a memory cell array, a bit line equalizer circuit, a PMOS sense amplifier (S/A), a PMOS S/A driving circuit for driving the PMOS S/A, a transmission gate circuit, an NMOS S/A, and an NMOS S/A driving circuit for driving the NMOS S/A. First and second transistors for connecting the local I/O lines to the global I/O lines are installed between adjacent bit lines. The PMOS S/A driving circuit, which is a first driving transistor, and the NMOS S/A driving circuit, which is a second driving transistor, are also installed between adjacent bit lines. Because the semiconductor memory device arranges a PMOS S/A driving circuit, an NMOS S/A driving circuit, and a gating circuit for connecting local I/O lines to global I/O lines, between adjacent bit lines, the chip area is reduced.
摘要翻译：提供了最小化芯片面积的半导体存储器件。半导体存储器件包括本地输入/输出（I / O）线，全局I / O线和耦合在位线和互补位线之间的存储器核。存储器芯包括存储单元阵列，位线均衡器电路，PMOS读出放大器（S / A），用于驱动PMOS S / A的PMOS S / A驱动电路，传输门电路，NMOS S / A 以及用于驱动NMOS S / A的NMOS S / A驱动电路。用于将本地I / O线连接到全局I / O线的第一和第二晶体管安装在相邻位线之间。作为第一驱动晶体管的PMOS S / A驱动电路和作为第二驱动晶体管的NMOS S / A驱动电路也安装在相邻位线之间。由于半导体存储器件在相邻位线之间配置PMOS S / A驱动电路，NMOS S / A驱动电路和用于将本地I / O线连接到全局I / O线的选通电路，芯片面积减小。

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