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    • 1. 发明申请
    • LIGHT DETECTION SYSTEM AND RELATED METHOD
    • 光检测系统及相关方法
    • US20090146981A1
    • 2009-06-11
    • US12104449
    • 2008-04-17
    • Chi-Wen ChenMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • Chi-Wen ChenMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • G09G5/00
    • G09G3/3406G09G2320/064G09G2360/144
    • The present invention provides a light detection system essentially including a light detection circuit for generating a light detection signal by performing a light detection process, an integration-period control circuit for generating a control signal based on the light detection signal, and an integration circuit for adjusting an integration period based on the control signal and generating a readout signal by performing an integration process on the light detection signal during the adjusted integration period. The present invention further provides a light detection method essentially including providing a plurality of integration periods, generating a light detection signal by performing a light detection process, selecting an integration period out of the provided integration periods based on the light detection signal, and generating a readout signal by performing an integration process on the light detection signal during the selected integration period.
    • 本发明提供一种光检测系统,其基本上包括:通过执行光检测处理产生光检测信号的光检测电路;基于光检测信号产生控制信号的积分周期控制电路;以及用于 基于所述控制信号调整积分期间,并通过在调整后的积分期间对所述光检测信号进行积分处理来生成读出信号。 本发明还提供了一种光检测方法,其基本上包括提供多个积分周期,通过执行光检测处理产生光检测信号,基于光检测信号从提供的积分周期中选择积分期,并产生 在所选择的积分期间对光检测信号进行积分处理。
    • 5. 发明授权
    • Shift register
    • 移位寄存器
    • US08031827B2
    • 2011-10-04
    • US13041794
    • 2011-03-07
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • G11C19/00
    • G11C19/28
    • A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
    • 移位寄存器包括多个级,{Sn},n = 1,2。 。 。 ,N,N为正整数。 在一个实施例中,每级Sn包括一个上拉电路,该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端,用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时,上拉控制电路响应地产生提供给输入节点Qn的信号,以接通上拉电路, 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路,以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2,并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。
    • 6. 发明申请
    • SHIFT REGISTER
    • 移位寄存器
    • US20110007863A1
    • 2011-01-13
    • US12877748
    • 2010-09-08
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • G11C19/00
    • G11C19/28
    • A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
    • 移位寄存器包括多个级,{Sn},n = 1,2。 。 。 ,N,N为正整数。 在一个实施例中,每级Sn包括一个上拉电路,该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端,用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时,上拉控制电路响应地产生提供给输入节点Qn的信号,以接通上拉电路, 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路,以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2,并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。
    • 7. 发明授权
    • Shift register
    • 移位寄存器
    • US07817771B2
    • 2010-10-19
    • US12334874
    • 2008-12-15
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • G11C19/00
    • G11C19/28
    • A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
    • 移位寄存器包括多个级,{Sn},n = 1,2。 。 。 ,N,N为正整数。 在一个实施例中,每级Sn包括一个上拉电路,该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端,用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时,上拉控制电路响应地产生提供给输入节点Qn的信号,以接通上拉电路, 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路,以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2,并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。
    • 9. 发明申请
    • Touch Panel
    • 触控面板
    • US20110018842A1
    • 2011-01-27
    • US12896911
    • 2010-10-03
    • Hsin-Hung LeePo-Yuan LiuMin-Feng ChiangChun-Hsin LiuChi-Wen Chen
    • Hsin-Hung LeePo-Yuan LiuMin-Feng ChiangChun-Hsin LiuChi-Wen Chen
    • G06F3/042
    • G06F3/0412G06F3/044G06F2203/04106
    • A touch panel includes a plurality of first pixels and second pixels. Each first pixel has a light sensing component for sensing light then generating a first sensing signal and a switch. The switch contains a first end coupled to the light sensing component, a control end for receiving a first gate driving signal, and a second end for transmitting the first sensing signal according to the first gate driving signal. Each second pixel includes a pressure sensing component for sensing pressure then generating a second sensing signal and a switch. The switch contains a first end coupled to the pressure sensing component, a control end for receiving a second gate driving signal, and a second end for transmitting the second sensing signal according to the second gate driving signal.
    • 触摸面板包括多个第一像素和第二像素。 每个第一像素具有用于感测光然后产生第一感测信号和开关的光感测部件。 开关包括耦合到光感测部件的第一端,用于接收第一栅极驱动信号的控制端和用于根据第一栅极驱动信号传输第一感测信号的第二端。 每个第二像素包括用于感测压力然后产生第二感测信号和开关的压力感测部件。 开关包括耦合到压力感测部件的第一端,用于接收第二栅极驱动信号的控制端和用于根据第二栅极驱动信号传输第二感测信号的第二端。