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1. 发明授权

US07319630B2 Current-limited latch 有权
标题翻译：电流限制闩锁
公开(公告)号：US07319630B2
公开(公告)日：2008-01-15
申请号：US11019990
申请日：2004-12-20
申请人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
发明人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
IPC分类号： G11C7/00
CPC分类号： G11C16/12
摘要： A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.
摘要翻译：在用于解码，编程，擦除和其他操作的非易失性存储器集成电路中使用限流锁存电路。在一个实现中，在两个电源线之间并联连接有多个锁存器。当前的镜像方案限制提供给锁存器的电流。在数据更改期间，可以减少两个电源，正电压，接地或负电压的差异。当锁存器中的数据变化时，该电路提供较小的器件尺寸和快速速度，同时还提供较低的功耗。当两个电源之间的电压差较大时，该技术提供了更大的益处。

2. 发明申请

US20050101236A1 Current-limited latch 有权
标题翻译：电流限制闩锁
公开(公告)号：US20050101236A1
公开(公告)日：2005-05-12
申请号：US11019990
申请日：2004-12-20
申请人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
发明人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
IPC分类号： G11C16/12 , B24D11/00
CPC分类号： G11C16/12
摘要： A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.
摘要翻译：用于解码，编程，擦除和其它操作的非易失性存储器集成电路中使用限流锁存电路。在一个实现中，在两个电源线之间并联连接有多个锁存器。当前的镜像方案限制提供给锁存器的电流。在数据更改期间，可以减少两个电源，正电压，接地或负电压的差异。当锁存器中的数据变化时，该电路提供较小的器件尺寸和快速速度，同时还提供较低的功耗。当两个电源之间的电压差较大时，该技术提供了更大的益处。

3. 发明授权

US07339822B2 Current-limited latch 有权
公开(公告)号：US07339822B2
公开(公告)日：2008-03-04
申请号：US10313738
申请日：2002-12-06
申请人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
发明人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.

4. 发明申请

US20060113619A1 Magnetic random access memory with reference magnetic resistance and reading method thereof 审中-公开
标题翻译：具有参考磁阻的磁性随机存取存储器及其读取方法
公开(公告)号：US20060113619A1
公开(公告)日：2006-06-01
申请号：US11224082
申请日：2005-09-13
申请人： Chien-Chung Hung , Yung-Hsiang Chen , Ming-Jer Kao , Kuo-Lung Chen , Lien-Chang Wang , Yung-Hung Wang
发明人： Chien-Chung Hung , Yung-Hsiang Chen , Ming-Jer Kao , Kuo-Lung Chen , Lien-Chang Wang , Yung-Hung Wang
IPC分类号： H01L43/00
CPC分类号： H01L43/08 , G11C11/15 , H01L27/228
摘要： A magnetic random access memory having reference magnetic resistance is provided. The memory includes at least one magnetic memory cell having an antiferromagnet layer, a pinned layer formed thereon, a tunnel barrier layer formed thereon, and a free layer formed thereon. The pinned layer and free layer are arranged orthogonally to form a reference magnetic resistance state. Through the provided MRAM structure, the access accuracy is greatly increased and the access speed is accelerated.
摘要翻译：提供具有参考磁阻的磁性随机存取存储器。存储器包括至少一个具有反铁磁体层，形成在其上的被钉扎层，形成在其上的隧道势垒层和形成在其上的自由层的磁存储单元。钉扎层和自由层正交布置以形成参考磁阻状态。通过提供的MRAM结构，访问精度大大提高，访问速度加快。

5. 发明授权

US5329487A Two transistor flash EPROM cell 失效
标题翻译：两个晶体管闪存EPROM单元
公开(公告)号：US5329487A
公开(公告)日：1994-07-12
申请号：US28042
申请日：1993-03-08
申请人： Anil Gupta , Kuo-Lung Chen
发明人： Anil Gupta , Kuo-Lung Chen
IPC分类号： G11C16/04 , H01L27/115 , G11C11/40
CPC分类号： G11C16/0441 , G11C16/0425 , H01L27/115
摘要： A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.
摘要翻译：双晶体管闪存EPROM单元包括用于对单元进行编程的第一浮栅晶体管和用于读取单元的第二合并晶体管。第一晶体管是浮栅晶体管，具有耦合到写位线的漏极，耦合到字线的栅极和耦合到源极线的源极。合并晶体管有效地由与NMOS增强晶体管串联的浮栅晶体管组成。串联NMOS晶体管具有约1至2伏特的电压阈值，从而防止由浮栅晶体管的过电压（负电压阈值）导致的电池激活。

6. 发明申请

US20070200188A1 Magnetic random access memory with reference magnetic resistance and reading method thereof 审中-公开
标题翻译：具有参考磁阻的磁性随机存取存储器及其读取方法
公开(公告)号：US20070200188A1
公开(公告)日：2007-08-30
申请号：US11797160
申请日：2007-05-01
申请人： Chien-Chung Hung , Yung-Hsiang Chen , Ming-Jer Kao , Kuo-Lung Chen , Lien-Chang Wang , Yung-Hung Wang
发明人： Chien-Chung Hung , Yung-Hsiang Chen , Ming-Jer Kao , Kuo-Lung Chen , Lien-Chang Wang , Yung-Hung Wang
IPC分类号： H01L43/00
CPC分类号： H01L43/08 , G11C11/15 , H01L27/228
摘要： A magnetic random access memory having reference magnetic resistance is provided. The memory includes at least one magnetic memory cell having an antiferromagnet layer, a pinned layer formed thereon, a tunnel barrier layer formed thereon, and a free layer formed thereon. The pinned layer and free layer are arranged orthogonally to form a reference magnetic resistance state. Through the provided MRAM structure, the access accuracy is greatly increased and the access speed is accelerated.
摘要翻译：提供具有参考磁阻的磁性随机存取存储器。存储器包括至少一个具有反铁磁体层，形成在其上的被钉扎层，形成在其上的隧道势垒层和形成在其上的自由层的磁存储单元。钉扎层和自由层正交布置以形成参考磁阻状态。通过提供的MRAM结构，访问精度大大提高，访问速度加快。

7. 发明授权

US07023726B1 Hybrid magnetoresistive random access memory (MRAM) architecture 失效
标题翻译：混合磁阻随机存取存储器（MRAM）架构
公开(公告)号：US07023726B1
公开(公告)日：2006-04-04
申请号：US11038107
申请日：2005-01-21
申请人： Kuo-Lung Chen , Ming-Jer Kao , Ming-Jin Tsai
发明人： Kuo-Lung Chen , Ming-Jer Kao , Ming-Jin Tsai
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： The present invention relates to a hybrid MRAM architecture, and more particularly to a hybrid MRAM architecture capable of being used with an MCU and an MPU. This hybrid MRAM architecture is adapted to a controlling device for accessing a bit of information, comprising a plurality of first MRAM arrays (1T1MTJ architecture), a plurality of second MRAM arrays (XPC architecture), an address line, an access decoder, a sensing and writing circuit, and at least one I/O bus. The access decoder accesses to the bit of information from either the first or the second MRAM arrays selected in accordance with an address signal from the controlling device. The sensing and writing circuit amplifies the bit of information and transmits it to the controlling device via the at least one I/O bus. Accordingly, the access of the bit of information is completed.
摘要翻译：混合MRAM架构技术领域本发明涉及混合MRAM架构，更具体地涉及能够与MCU和MPU一起使用的混合MRAM架构。该混合MRAM架构适用于访问一比特信息的控制设备，包括多个第一MRAM阵列（1T1MTJ架构），多个第二MRAM阵列（XPC架构），地址线，接入解码器，感测和写入电路，以及至少一个I / O总线。接入解码器根据来自控制设备的地址信号选择的第一或第二MRAM阵列访问信息比特。感测和写入电路放大信息比特，并通过至少一个I / O总线将其发送到控制设备。因此，信息位的访问完成。

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