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1. 发明申请

US20080111284A1 Method of manufacturing a molding structure, and method and apparatus for molding a substrate using the molding structure 审中-公开
标题翻译：模制结构的制造方法以及使用该模制结构模制基材的方法和装置
公开(公告)号：US20080111284A1
公开(公告)日：2008-05-15
申请号：US11985146
申请日：2007-11-14
申请人： Cheol-Joon Yoo , Tae-Sung Yoon
发明人： Cheol-Joon Yoo , Tae-Sung Yoon
IPC分类号： B29C43/18
CPC分类号： B29C43/183 , B29C33/68 , B29C43/146 , B29C2043/3411 , B29C2043/3605 , B29K2105/251 , B29L2031/772 , H05K3/0014
摘要： In a method of molding a substrate, a molding structure including a release film and flat plate-shaped epoxy molding compound (EMC) is placed on an upper face of a lower die. The substrate is held by a lower face of an upper die facing the lower die. The molding structure and the substrate are compressed using the lower die and the upper die to form a preliminarily molded substrate. The lower die is then downwardly moved from the upper die to form a molded substrate.
摘要翻译：在成型基板的方法中，将包含脱模膜和平板状环氧树脂模塑料（EMC）的模制结构放置在下模的上表面上。基板由面向下模的上模的下表面保持。使用下模和上模压缩成形结构和基板，以形成预成型基板。然后将下模从上模向下移动以形成模制基板。

2. 发明授权

US07485959B2 Structure for joining a semiconductor package to a substrate using a solder column 有权
标题翻译：使用焊料柱将半导体封装与基板接合的结构
公开(公告)号：US07485959B2
公开(公告)日：2009-02-03
申请号：US11330773
申请日：2006-01-11
申请人： Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
发明人： Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H05K3/3436 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/13 , H01L2224/13099 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H05K3/3452 , H05K3/3484 , H05K2201/10977 , H05K2203/0568 , Y02P70/613 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a package mounting substrate can be joined using a conductive material column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. The insulating protective openings protect the solder column against stress faults to form reliable electrical connections and to support high-density electrical connections between the semiconductor package and the package mounting substrate.
摘要翻译：半导体封装和封装安装基板可以使用导电材料柱接合。半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。焊料柱位于绝缘保护开口内，以电连接布线层。绝缘保护开口保护焊料柱免受应力故障的影响，形成可靠的电连接并支持半导体封装和封装安装基板之间的高密度电连接。

3. 发明申请

US20060157848A1 Structure and method for joining a semiconductor package to a substrate using solder column 有权
标题翻译：使用焊料柱将半导体封装与基板接合的结构和方法
公开(公告)号：US20060157848A1
公开(公告)日：2006-07-20
申请号：US11330773
申请日：2006-01-11
申请人： Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
发明人： Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H05K3/3436 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/13 , H01L2224/13099 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H05K3/3452 , H05K3/3484 , H05K2201/10977 , H05K2203/0568 , Y02P70/613 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a semiconductor package and a package mounting substrate are joined using a conductive material column such as a solder column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. By forming the insulating protective openings with sufficient depth, each protects the solder column against stress faults and thereby forms more reliable electrical connections and supports high-density electrical connections between the semiconductor package and the package mounting substrate.
摘要翻译：在一个实施例中，使用诸如焊料柱的导电材料柱将半导体封装和封装安装基板接合。半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。焊料柱位于绝缘保护开口内，以电连接布线层。通过形成具有足够深度的绝缘保护开口，每个保护焊料柱免受应力故障，从而形成更可靠的电连接并且支持半导体封装和封装安装基板之间的高密度电连接。

4. 发明授权

US07368821B2 BGA semiconductor chip package and mounting structure thereof 失效
标题翻译： BGA半导体芯片封装及其安装结构
公开(公告)号：US07368821B2
公开(公告)日：2008-05-06
申请号：US11231751
申请日：2005-09-22
申请人： Sang-Young Kim , Jin-Ho Kim , Hee-Jin Park , Young-Hee Song , Tae-Sung Yoon
发明人： Sang-Young Kim , Jin-Ho Kim , Hee-Jin Park , Young-Hee Song , Tae-Sung Yoon
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H05K3/303 , H05K3/3436 , H05K3/3452 , H05K2201/094 , H05K2201/09781 , H05K2201/10734 , H05K2201/2036 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy solder balls provided on the second surface of the substrate, wherein the I/O solder balls are electrically connected to the semiconductor chip and the dummy solder balls are electrically isolated from the semiconductor chip, and the I/O solder balls and the dummy solder balls have the same ball size and ball pitch and are uniformly provided over the second surface of the substrate.
摘要翻译：在本发明的示例性实施例中，BGA半导体芯片封装的结构包括具有第一和第二表面的衬底，具有多个焊盘的半导体芯片，并且安装在衬底的第一表面上，以及多个入/ （I / O）焊球和设置在基板的第二表面上的虚拟焊球，其中I / O焊球电连接到半导体芯片，并且虚拟焊球与半导体芯片电隔离，并且 I / O焊球和虚拟焊球具有相同的球尺寸和球间距，并均匀地设置在基板的第二表面上。

5. 发明授权

US08294250B2 Wiring substrate for a semiconductor chip, and semiconducotor package having the wiring substrate 有权
标题翻译：用于半导体芯片的布线基板和具有布线基板的半导体封装
公开(公告)号：US08294250B2
公开(公告)日：2012-10-23
申请号：US12901129
申请日：2010-10-08
申请人： Tae-Sung Yoon
发明人： Tae-Sung Yoon
IPC分类号： H01L23/02
CPC分类号： H01L24/49 , H01L23/13 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L24/48 , H01L2224/05554 , H01L2224/32225 , H01L2224/48106 , H01L2224/48108 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/49433 , H01L2224/73215 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A wiring substrate for a semiconductor chip includes a substrate, first and second wiring layers and a plurality of first and second bonding pads. The substrate has a first surface and a second surface opposite to the first surface, a window extending from the first surface to the second surface to expose chip pads of a semiconductor chip adherable to the first surface. The first and second wiring layers of a multi-layered structure are sequentially formed on the second surface of the substrate with at least one insulation layer interposed between the first and second wiring layers. A plurality of the first and second bonding pads are respectively connected to the first and second wiring layers, the first and second bonding pads having a concavo-convex arrangement on the second surface of the substrate along a side of the window.
摘要翻译：用于半导体芯片的布线基板包括基板，第一和第二布线层以及多个第一和第二接合焊盘。衬底具有与第一表面相对的第一表面和第二表面，从第一表面延伸到第二表面的窗口，以暴露可粘附到第一表面的半导体芯片的芯片焊盘。多层结构的第一和第二布线层依次形成在衬底的第二表面上，其中至少一个绝缘层介于第一和第二布线层之间。多个第一和第二接合焊盘分别连接到第一和第二布线层，第一和第二接合焊盘在基板的沿着窗的一侧的第二表面上具有凹凸布置。

6. 发明申请

US20110084410A1 Wiring Substrate for a Semiconductor Chip, and Semiconducotor Package Having the Wiring Substrate 有权
标题翻译：用于半导体芯片的接线基板和具有接线基板的半导体封装
公开(公告)号：US20110084410A1
公开(公告)日：2011-04-14
申请号：US12901129
申请日：2010-10-08
申请人： Tae-Sung Yoon
发明人： Tae-Sung Yoon
IPC分类号： H01L23/52 , H01L23/535
CPC分类号： H01L24/49 , H01L23/13 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L24/48 , H01L2224/05554 , H01L2224/32225 , H01L2224/48106 , H01L2224/48108 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/49433 , H01L2224/73215 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A wiring substrate for a semiconductor chip includes a substrate, first and second wiring layers and a plurality of first and second bonding pads. The substrate has a first surface and a second surface opposite to the first surface, a window extending from the first surface to the second surface to expose chip pads of a semiconductor chip adherable to the first surface. The first and second wiring layers of a multi-layered structure are sequentially formed on the second surface of the substrate with at least one insulation layer interposed between the first and second wiring layers. A plurality of the first and second bonding pads are respectively connected to the first and second wiring layers, the first and second bonding pads having a concavo-convex arrangement on the second surface of the substrate along a side of the window.
摘要翻译：用于半导体芯片的布线基板包括基板，第一和第二布线层以及多个第一和第二接合焊盘。衬底具有与第一表面相对的第一表面和第二表面，从第一表面延伸到第二表面的窗口，以暴露可粘附到第一表面的半导体芯片的芯片焊盘。多层结构的第一和第二布线层依次形成在衬底的第二表面上，其中至少一个绝缘层介于第一和第二布线层之间。多个第一和第二接合焊盘分别连接到第一和第二布线层，第一和第二接合焊盘在基板的沿着窗的一侧的第二表面上具有凹凸布置。

7. 发明申请

US20070007645A1 Stack package and semiconductor module implementing the same 失效
标题翻译：堆栈封装和半导体模块实现相同
公开(公告)号：US20070007645A1
公开(公告)日：2007-01-11
申请号：US11331001
申请日：2006-01-13
申请人： Tae-Sung Yoon
发明人： Tae-Sung Yoon
IPC分类号： H01L23/34
CPC分类号： H01L25/105 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/49109 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/107 , H01L2924/01079 , H01L2924/15311 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/48227
摘要： The stack package may have a structure in which unit packages may be inserted into slots of a receiving substrate. The unit package may have a plurality of connecting pads. The receiving substrate may have substrate pads, which may be electrically connected to the connecting pads of the unit packages inserted in the slots by mechanical contact. The slots may be provided at regular vertical intervals so that the unit packages may be stacked in the vertical direction. A semiconductor module may include stack packages installed on at least one surface of a module substrate.
摘要翻译：堆叠封装可以具有其中单元封装可以插入到接收衬底的槽中的结构。单元封装可以具有多个连接焊盘。接收基板可以具有衬底焊盘，其可以通过机械接触电连接到插入插槽中的单元封装的连接焊盘。槽可以以规则的垂直间隔设置，使得单元包可以在垂直方向上堆叠。半导体模块可以包括安装在模块基板的至少一个表面上的堆叠封装。

8. 发明申请

US20080187613A1 Method of manufacturing wafer-level chip-size package and molding apparatus used in the method 审中-公开
标题翻译：本方法中使用的晶圆级芯片尺寸封装和成型装置的制造方法
公开(公告)号：US20080187613A1
公开(公告)日：2008-08-07
申请号：US12078638
申请日：2008-04-02
申请人： Tae-Sung Yoon
发明人： Tae-Sung Yoon
IPC分类号： B29C45/03 , B29C45/14
CPC分类号： B29C43/36 , B29C43/32 , H01L23/3114 , H01L2224/16 , H01L2224/274
摘要： Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer having a plurality of semiconductor chips formed thereon may be encapsulated. The semiconductor wafer, typically with a plurality of conductive bumps extending from the semiconductor chips, will be placed in a cavity formed between upper and lower molds. Injection molding of an encapsulant composition or compression molding of encapsulant sheets may then be used to apply encapsulating layers to the upper and lower surfaces of the semiconductor wafer in a substantially simultaneous manner, thereby reducing the likelihood of warping and mechanical damage to the semiconductor wafer. The wafer-level chip-size packages can then be separated from the encapsulated semiconductor wafer.
摘要翻译：提供一种制造晶片级芯片尺寸封装的方法和适于实施其上可形成其上形成有多个半导体芯片的半导体晶片的方法的成型装置。通常具有从半导体芯片延伸的多个导电凸块的半导体晶片将被放置在形成在上模和下模之间的空腔中。密封剂组合物的注射成型或密封片的压塑可以用于以基本上同时的方式将包封层施加到半导体晶片的上表面和下表面，从而减少翘曲和对半导体晶片的机械损伤的可能性。然后可以将晶片级芯片尺寸封装与封装的半导体晶片分离。

9. 发明授权

US07327032B2 Semiconductor package accomplishing fan-out structure through wire bonding 有权
标题翻译：半导体封装通过引线键合实现扇出结构
公开(公告)号：US07327032B2
公开(公告)日：2008-02-05
申请号：US11279344
申请日：2006-04-11
申请人： Tae-Sung Yoon
发明人： Tae-Sung Yoon
IPC分类号： H01L23/48 , H01L23/28
CPC分类号： H01L24/73 , H01L23/3114 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/5389 , H01L24/48 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/131 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/484 , H01L2224/73265 , H01L2224/85399 , H01L2224/8592 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.
摘要翻译：提供一种通过引线接合实现扇出结构的半导体封装，其中半导体芯片的焊盘通过引线接合连接到印刷电路板。半导体封装可以在没有模制工艺的情况下制造，并且可以容易地堆叠在另一个半导体封装上，同时可以防止外观破裂和翘曲缺陷。

10. 发明授权

US06946328B2 Method for manufacturing semiconductor devices 失效
公开(公告)号：US06946328B2
公开(公告)日：2005-09-20
申请号：US10866662
申请日：2004-06-15
申请人： Pyoung-Wan Kim , Tae-Sung Yoon , Hyeon Hwang
发明人： Pyoung-Wan Kim , Tae-Sung Yoon , Hyeon Hwang
IPC分类号： H01L21/52 , H01L21/304 , H01L21/44 , H01L21/58 , H01L21/68 , H01L21/78 , H01L21/98 , H01L25/065
CPC分类号： H01L21/6836 , H01L21/78 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/274 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29298 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/92 , H01L2224/92247 , H01L2225/0651 , H01L2225/06568 , H01L2225/06575 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/01028 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： A method for manufacturing semiconductor devices is provided in which an organic adhesive layer is formed on the backside of a semiconductor wafer after being thinned by a backlapping process and cured to form a B-stage adhesive layer. Using the B-stage adhesive layer, the semiconductor device may then be attached to a circuit substrate and then subjected to additional curing to form a C-stage adhesive layer. Such semiconductor devices may also be attached directly to a lower semiconductor chip or, in the alternative, may be attached to a spacer mounted that is or will be mounted on a lower semiconductor chip or the circuit substrate. The organic adhesive is selected to counteract stresses induced by a passivation layer formed on the active surface, thereby reducing or preventing warping of the semiconductor wafer and eliminating the need for a separate resin paste adhesive during the chip attaching process.

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