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1. 发明授权

US08232152B2 Removing method of a hard mask 有权
标题翻译：去除硬掩模的方法
公开(公告)号：US08232152B2
公开(公告)日：2012-07-31
申请号：US12883233
申请日：2010-09-16
申请人： Che-Hua Hsu , Shao-Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
发明人： Che-Hua Hsu , Shao-Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/823456 , H01L21/823468 , H01L29/6656
摘要： A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.
摘要翻译：硬掩模的去除方法包括以下步骤。提供基板。在衬底上形成至少两个MOSFET。在衬底中形成隔离结构，并且位于至少两个MOSFET之间。 MOSEFT中的每一个在栅极上包括栅极绝缘层，栅极，间隔物和硬掩模。在隔离结构上形成保护结构，从保护结构露出硬掩模。暴露的硬掩模被移除以露出门。

2. 发明申请

US20120070952A1 REMOVING METHOD OF A HARD MASK 有权
标题翻译：硬掩模的拆卸方法
公开(公告)号：US20120070952A1
公开(公告)日：2012-03-22
申请号：US12883233
申请日：2010-09-16
申请人： Che-Hua HSU , Shao- Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
发明人： Che-Hua HSU , Shao- Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/823456 , H01L21/823468 , H01L29/6656
摘要： A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.
摘要翻译：硬掩模的去除方法包括以下步骤。提供基板。在衬底上形成至少两个MOSFET。在衬底中形成隔离结构，并且位于至少两个MOSFET之间。 MOSEFT中的每一个在栅极上包括栅极绝缘层，栅极，间隔物和硬掩模。在隔离结构上形成保护结构，从保护结构露出硬掩模。暴露的硬掩模被移除以露出门。

3. 发明授权

US08709930B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08709930B2
公开(公告)日：2014-04-29
申请号：US13304416
申请日：2011-11-25
申请人： Zen-Jay Tsai , Shao-Hua Hsu , Chi-Horn Pai , Ying-Hung Chou , Shih-Hao Su , Shih-Chieh Hsu , Chih-Ho Wang , Hung-Yi Wu , Shui-Yen Lu
发明人： Zen-Jay Tsai , Shao-Hua Hsu , Chi-Horn Pai , Ying-Hung Chou , Shih-Hao Su , Shih-Chieh Hsu , Chih-Ho Wang , Hung-Yi Wu , Shui-Yen Lu
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/51 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7843
摘要： A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.
摘要翻译：提供半导体工艺。前述步骤包括：在基板上形成包括第一盖层的第一栅极和包括第二盖层的第二栅极。形成硬掩模层以覆盖第一栅极和第二栅极。硬掩模层的材料与第一盖层和第二盖层的材料不同。在光刻工艺和蚀刻工艺进行之后，硬掩模层被完全去除。以下步骤包括：形成材料以完全覆盖第一栅极和第二栅极。材料，第一栅极和第二栅极被回蚀，以使第一栅极和第二栅极具有相同的电平并且在它们两者中暴露层。

4. 发明申请

US20130137256A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130137256A1
公开(公告)日：2013-05-30
申请号：US13304416
申请日：2011-11-25
申请人： Zen-Jay Tsai , Shao-Hua Hsu , Chi-Horn Pai , Ying-Hung Chou , Shih-Hao Su , Shih-Chieh Hsu , Chih-Ho Wang , Hung-Yi Wu , Shui-Yen Lu
发明人： Zen-Jay Tsai , Shao-Hua Hsu , Chi-Horn Pai , Ying-Hung Chou , Shih-Hao Su , Shih-Chieh Hsu , Chih-Ho Wang , Hung-Yi Wu , Shui-Yen Lu
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/51 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7843
摘要： A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.
摘要翻译：提供半导体工艺。前述步骤包括：在基板上形成包括第一盖层的第一栅极和包括第二盖层的第二栅极。形成硬掩模层以覆盖第一栅极和第二栅极。硬掩模层的材料与第一盖层和第二盖层的材料不同。在光刻工艺和蚀刻工艺进行之后，硬掩模层被完全去除。以下步骤包括：形成材料以完全覆盖第一栅极和第二栅极。材料，第一栅极和第二栅极被回蚀，以使第一栅极和第二栅极具有相同的电平并且在它们两者中暴露层。

5. 发明授权

US08801446B2 Connector assembly 有权
标题翻译：连接器组件
公开(公告)号：US08801446B2
公开(公告)日：2014-08-12
申请号：US13678870
申请日：2012-11-16
申请人： Hung-Yi Wu , Lei Liu
发明人： Hung-Yi Wu , Lei Liu
IPC分类号： H01R27/00
CPC分类号： H05K3/32 , H01R9/03 , H01R12/58 , H01R27/00 , H05K2201/10295
摘要： A connector assembly includes a female connector and a mal connector. The female connector includes a first main body and a number of slots defined in the first main body, and each slot receives a conductive terminal therein. First and second row conductive terminals are arranged along an opposite direction. A number of cables are attached to the first main body and electrically connected to the conductive terminals. A male connector includes a second main body and a number of conductive pins extend through the second main body. Third row conductive pins are corresponding to the first row conductive terminals. Fourth row conductive pins are corresponding to the second row conductive terminals. The connector assembly can transmit signals normally whatever the male connector is plugged to the female connector.
摘要翻译：连接器组件包括阴连接器和连接器。阴连接器包括第一主体和限定在第一主体中的多个狭槽，并且每个狭槽在其中容纳导电端子。第一和第二行导电端子沿相反方向布置。多个电缆连接到第一主体并电连接到导电端子。阳连接器包括第二主体，并且多个导电销延伸穿过第二主体。第三行导电引脚对应于第一行导电端子。第四行导电引脚对应于第二行导电端子。连接器组件可以正常传输任何公连接器插入母连接器的信号。

6. 发明授权

US08476004B2 Method for forming photoresist patterns 有权
标题翻译：光刻胶图形形成方法
公开(公告)号：US08476004B2
公开(公告)日：2013-07-02
申请号：US13169045
申请日：2011-06-27
申请人： Yong-Fa Huang , Cheng-Han Wu , Yuan-Chi Pai , Chun-Chi Yu , Hung-Yi Wu
发明人： Yong-Fa Huang , Cheng-Han Wu , Yuan-Chi Pai , Chun-Chi Yu , Hung-Yi Wu
IPC分类号： G03F7/26
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/095 , G03F7/168 , G03F7/2041
摘要： A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index.
摘要翻译：形成光致抗蚀剂图案的方法包括提供衬底，在衬底上形成双层光致抗蚀剂，以及执行光刻工艺以对双层光致抗蚀剂进行图案化。双层光致抗蚀剂包括第一光致抗蚀剂层和位于第一光致抗蚀剂层和基底之间的第二光致抗蚀剂层。第一光致抗蚀剂层具有第一折射率，第二光致抗蚀剂层具有第二折射率，第二折射率大于第一折射率。

7. 发明申请

US20120329280A1 METHOD FOR FORMING PHOTORESIST PATTERNS 有权
标题翻译：形成光电子图案的方法
公开(公告)号：US20120329280A1
公开(公告)日：2012-12-27
申请号：US13169045
申请日：2011-06-27
申请人： Yong-Fa Huang , Cheng-Han Wu , Yuan-Chi Pai , Chun-Chi Yu , Hung-Yi Wu
发明人： Yong-Fa Huang , Cheng-Han Wu , Yuan-Chi Pai , Chun-Chi Yu , Hung-Yi Wu
IPC分类号： H01L21/311
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/095 , G03F7/168 , G03F7/2041
摘要： A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index.
摘要翻译：形成光致抗蚀剂图案的方法包括提供衬底，在衬底上形成双层光致抗蚀剂，并执行光刻工艺以对双层光致抗蚀剂进行图案化。双层光致抗蚀剂包括第一光致抗蚀剂层和位于第一光致抗蚀剂层和基底之间的第二光致抗蚀剂层。第一光致抗蚀剂层具有第一折射率，第二光致抗蚀剂层具有第二折射率，第二折射率大于第一折射率。

8. 发明授权

US08514584B2 Serial advanced technology attachment DIMM device 失效
标题翻译：串行高级技术附件DIMM设备
公开(公告)号：US08514584B2
公开(公告)日：2013-08-20
申请号：US13198866
申请日：2011-08-05
申请人： An-Gang Liang , Hung-Yi Wu
发明人： An-Gang Liang , Hung-Yi Wu
IPC分类号： H05K1/14
CPC分类号： G06F1/185
摘要： A serial advanced technology attachment (SATA) DIMM device includes a board body. A control chip is arranged on the board body. First and second extending boards extend from an end of the board body and a space is defined between the first and the second extending boards. A first edge connector is set on the first extending board and a second edge connector is set on the bottom edges of the second extending board and the board body. The first edge connector includes a number of signal pins connected to the control chip, and a number of ground pins.
摘要翻译：串行高级技术附件（SATA）DIMM设备包括板体。控制芯片布置在板体上。第一和第二延伸板从板体的端部延伸，并且在第一和第二延伸板之间限定空间。第一边缘连接器设置在第一延伸板上，并且第二边缘连接器设置在第二延伸板和板体的底部边缘上。第一边缘连接器包括连接到控制芯片的多个信号引脚和多个接地引脚。

9. 发明授权

US08072157B2 Circuit for driving LED 失效
标题翻译： LED驱动电路
公开(公告)号：US08072157B2
公开(公告)日：2011-12-06
申请号：US12494287
申请日：2009-06-30
申请人： Xiao-Zhu Chen , Hung-Yi Wu , Lei Liu
发明人： Xiao-Zhu Chen , Hung-Yi Wu , Lei Liu
IPC分类号： H05B37/02
CPC分类号： H05B33/0818 , Y02B20/346
摘要： A circuit for driving a light emitting diode (LED), the circuit includes a timer, first to third electronic switches, and a regulator. The timer provides a pulse signal to switch the first and second electronic switches. The first electronic switch provides a first level signal to one end of the LED. The second electronic switch switches the third electronic switch on and off. The third electronic switch provides a third level signal to another end of the LED. The regulator adjusts the pulse signal to be at a predetermined frequency to control the first, second, and the third level signals to alternate between a high voltage level and a low voltage level at the predetermined frequency. The LED is driven to be on and off at the predetermined frequency by the first and third level signals.
摘要翻译：一种用于驱动发光二极管（LED）的电路，该电路包括定时器，第一至第三电子开关和调节器。定时器提供脉冲信号以切换第一和第二电子开关。第一个电子开关向LED的一端提供一级信号。第二个电子开关打开和关闭第三个电子开关。第三个电子开关向LED的另一端提供第三电平信号。调节器将脉冲信号调整到预定频率，以控制第一，第二和第三电平信号在预定频率的高电压电平和低电压电平之间交替。通过第一和第三电平信号以预定频率驱动LED被开启和关闭。

10. 发明授权

US07995341B2 Electronic device with heat dissipating mechanism 失效
标题翻译：具有散热机构的电子装置
公开(公告)号：US07995341B2
公开(公告)日：2011-08-09
申请号：US12727242
申请日：2010-03-19
申请人： Hung-Yi Wu , Xiao-Zhu Chen
发明人： Hung-Yi Wu , Xiao-Zhu Chen
IPC分类号： H05K7/20
CPC分类号： G06F1/26 , G06F1/181 , G06F1/20
摘要： An electronic device includes a base and a sidewall attached to the base. The sidewall includes a heat dissipating area defining a plurality of vents, a sliding plate slidably coupled to an inner side of the sidewall, and a controlling arm made of metal material having high coefficient of thermal expansion. The controlling arm is connected between the sliding plate and the sidewall, for driving the sliding plate to slide to cover or uncover the vents of the heat dissipating area according to different interior temperature of the electronic device.
摘要翻译：电子设备包括底座和附接到底座的侧壁。侧壁包括限定多个通风口的散热区域，可滑动地联接到侧壁的内侧的滑动板和由具有高热膨胀系数的金属材料制成的控制臂。控制臂连接在滑动板和侧壁之间，用于驱动滑板滑动以根据电子设备的不同内部温度来覆盖或露出散热区域的通风口。

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