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1. 发明授权

US5359496A Hermetic high density interconnected electronic system 失效
标题翻译：密封高密度互联电子系统
公开(公告)号：US5359496A
公开(公告)日：1994-10-25
申请号：US67157
申请日：1993-05-26
申请人： William P. Kornrumpf , Robert J. Wojnarowski , Charles W. Eichelberger
发明人： William P. Kornrumpf , Robert J. Wojnarowski , Charles W. Eichelberger
IPC分类号： H01L23/02 , H01L21/58 , H01L23/04 , H01L23/10 , H01L23/538 , H01L23/552 , H01L25/065 , H05K1/11
CPC分类号： H01L24/83 , H01L23/04 , H01L23/10 , H01L23/5383 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/29 , H01L24/82 , H01L25/0655 , H01L2224/24137 , H01L2224/24225 , H01L2224/24227 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2224/82039 , H01L2224/8319 , H01L2224/8385 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H01L2924/16152 , H01L2924/3025
摘要： A body is hermetically sealed by electroplating a hermetic layer over the exterior surface of the body. A hermetic high density interconnect structure is provided by forming a continuous metal layer over the outermost dielectric layer of the multilayer interconnect structure and by disposing that continuous metal layer in a hermetically sealing relation to the substrate of the high density interconnect structure. A variety of techniques may be used for providing electrical feedthroughs between the interior and exterior of the hermetic enclosure as may a pseudo-hermetic enclosure in those situations where true hermeticity is not required.
摘要翻译：通过在身体的外表面上电镀一层密封层，使身体密封。通过在多层互连结构的最外层电介质层上形成连续的金属层，并通过将该连续金属层与高密度互连结构的衬底密封地设置，来提供密封的高密度互连结构。可以使用各种技术来在密封外壳的内部和外部之间提供电馈通，如在不需要真实气密的那些情况下的伪密封封壳。

2. 发明授权

US5348607A High density interconnect thermoplastic die attach material and solvent die attach processing 失效
标题翻译：高密度互连热塑性管芯附着材料和溶剂管芯附着加工
公开(公告)号：US5348607A
公开(公告)日：1994-09-20
申请号：US20913
申请日：1993-02-22
申请人： Robert J. Wojnarowski , Charles W. Eichelberger
发明人： Robert J. Wojnarowski , Charles W. Eichelberger
IPC分类号： H01L21/58 , H01L23/538 , B32B31/00
CPC分类号： H01L24/83 , H01L23/5389 , H01L24/29 , H01L2224/2919 , H01L2224/8319 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/19041 , Y10T156/109 , Y10T156/1092 , Y10T156/1111
摘要： A mixture for affixing dice to a substrate includes a thermoplastic polyimide, a solvent for the polyimide, and a solvent which does not dissolve the polyimide but adds thixotropicity to the mixture. The mixture is applied to the substrate, the dice are placed thereon, and the solvents are evaporated to bond the dice to the substrate. The bond is radiation hard and exhibits high shear pull strength. A poor solvent for the polyimide, sprayed over the dice and exposed portions of die attach material, causes some polyimide to precipitate out of solution in the exposed portions of die attach material to form a grid that extends between the dice and prevents the dice from "swimming together" during high temperature processing. In a solvent die-attachment method, the substrate is first coated with a mixture of die attach material, and the mixture is dried. Spraying a solvent over the die attach material causes the material to soften so that the dice applied thereto may adhere. The die attach material is then dried to form the bond.
摘要翻译：用于将骰子固定到基底的混合物包括热塑性聚酰亚胺，聚酰亚胺的溶剂和不溶解聚酰亚胺但对混合物具有触变性的溶剂。将混合物施加到基底上，将骰子放置在其上，并蒸发溶剂以将骰子结合到基底。该粘合剂是辐射硬的并且表现出高的剪切拉力。用于聚酰亚胺的不良溶剂喷涂在芯片附着材料的骰子和暴露部分上，导致一些聚酰亚胺从裸片附着材料的暴露部分中沉淀出溶液中以形成在骰子之间延伸的网格，并防止骰子“ 在高温加工过程中一起游泳。在溶剂模具附着方法中，首先用基片附着材料的混合物涂覆基板，并将混合物干燥。在模具附着材料上喷涂溶剂导致材料软化，使得施加到其上的骰子可以粘附。然后将管芯附着材料干燥以形成粘合。

3. 发明授权

US5157589A Mutliple lamination high density interconnect process and structure employing thermoplastic adhesives having sequentially decreasing T.sub.G ' s 失效
标题翻译： MUTLIPLE LAMINATION高密度互连过程和结构使用具有顺序降低的热塑性粘合剂
公开(公告)号：US5157589A
公开(公告)日：1992-10-20
申请号：US546963
申请日：1990-07-02
申请人： Herbert S. Cole, Jr. , James W. Rose , Charles W. Eichelberger , Robert J. Wojnarowski
发明人： Herbert S. Cole, Jr. , James W. Rose , Charles W. Eichelberger , Robert J. Wojnarowski
IPC分类号： H01L23/13 , H01L23/498 , H01L23/538 , H01L25/04 , H01L25/18 , H05K1/18 , H05K3/38 , H05K3/46
CPC分类号： H01L23/5389 , H01L23/13 , H01L23/49822 , H01L24/24 , H01L24/82 , H05K3/4635 , H05K3/4673 , H01L2224/2402 , H01L2224/24227 , H01L2224/73267 , H01L2224/82039 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01082 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H05K1/185 , H05K2201/0129 , H05K2201/0154 , H05K2201/0195 , H05K3/386 , H05K3/4644
摘要： A high density interconnect structure incorporating a plurality of laminated dieletric layers is fabricated using thermoplastic adhesive layers of progressively lower glass transition temperature in order to maintain the stability of the already fabricated structure during the addition of the later laminations. This structure also facilitates the removal of only a portion of the high density interconnect structure where a fault in the system can be corrected in one of the upper layers of the high density interconnect structure.

4. 发明授权

US4842677A Excimer laser patterning of a novel resist using masked and maskless process steps 失效
标题翻译：使用掩蔽和无掩模工艺步骤的新型抗蚀剂的准分子激光图案化
公开(公告)号：US4842677A
公开(公告)日：1989-06-27
申请号：US224416
申请日：1988-07-26
申请人： Robert J. Wojnarowski , Charles W. Eichelberger
发明人： Robert J. Wojnarowski , Charles W. Eichelberger
IPC分类号： G03F7/11 , G03F7/095 , G03F7/20 , G03F7/26 , H01L21/027 , H01L23/538 , H05K3/00 , H05K3/06
CPC分类号： H05K3/0082 , G03F7/095 , G03F7/2006 , H01L23/5389 , H01L2924/0002 , H05K2203/0505 , H05K2203/0577 , H05K2203/107 , H05K3/0032 , H05K3/064
摘要： A dual layer resist configuration is employed for photopatterning high resolution conductive patterns on underlying polymeric or ceramic substrates, particularly substrates exhibiting surface roughness and non-planar design features such as channels, bosses and ridges. More particularly, a thin underlayer of ablatable photoabsorptive polymer is disposed on a metal coated substrate, after which a thicker layer of substantially transparent material is disposed over the polymer. A beam of laser energy, such as that produced by an ultraviolet excimer layer, is directed through the upper layer and is absorbed by the lower layer which is ablated and simultaneously removes the thick layer above it. This results in the ability to etch high resolution features on polymeric and other substrates, particularly copper coated polyetherimide circuit boards. The resist system is also applicable to VLSI wafers even though such wafers usually do not exhibit surface roughness on the scale generally considered herein. It is also equally applicable in various high density interconnect systems used for the direct connection of chip devices. A mask for patterning and a method for making it are also seen to be desirable because of the high laser energy densities generally desired for thorough ablation. An alternate method is also disclosed which employs two laser exposure steps with the first step being a masked operation on only an ablatable layer and with the second step being an unmasked operation on a dual layer material.

5. 发明授权

US4783695A Multichip integrated circuit packaging configuration and method 失效
标题翻译：多芯片集成电路封装配置和方法
公开(公告)号：US4783695A
公开(公告)日：1988-11-08
申请号：US912456
申请日：1986-09-26
申请人： Charles W. Eichelberger , Robert J. Wojnarowski
发明人： Charles W. Eichelberger , Robert J. Wojnarowski
IPC分类号： H01L25/18 , H01L21/60 , H01L23/52 , H01L23/538 , H01L25/04 , H01L23/48
CPC分类号： H01L24/75 , H01L23/5385 , H01L23/5387 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/2402 , H01L2224/24137 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/75315 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107
摘要： A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.
摘要翻译：多芯片集成电路封装包括一个衬底，一个或多个具有互连焊盘的集成电路芯片。覆盖和桥接存在的集成电路芯片的聚合物膜设置有多个通孔以容纳互连金属化层，其用于连接布置在芯片上的互连焊盘内的各种芯片和芯片焊盘。本发明的包装方法和结构的显着优点是除去聚合物膜的能力。这显着提高了可测试性，并有效提供了没有与产量和可测试性相关的问题的晶片级集成电路封装。

6. 发明授权

US4714516A Method to produce via holes in polymer dielectrics for multiple electronic circuit chip packaging 失效
标题翻译：在多电子电路芯片封装的聚合物电介质中制造通孔的方法
公开(公告)号：US4714516A
公开(公告)日：1987-12-22
申请号：US912455
申请日：1986-09-26
申请人： Charles W. Eichelberger , Robert J. Wojnarowski
发明人： Charles W. Eichelberger , Robert J. Wojnarowski
IPC分类号： B05D3/06 , B23K26/00 , B29C59/14 , C08J7/00 , H01L21/48 , H01L23/538 , H05K3/00 , H05K3/46 , B44C1/22 , B29C37/00 , C03C15/00 , C03C25/06
CPC分类号： H05K3/0041 , B23K26/0006 , B23K26/362 , H01L21/4803 , H01L23/5389 , H05K3/0035 , B23K2201/34 , B23K2201/42 , B23K2203/172 , B23K2203/42 , B23K2203/50 , H01L2924/0002 , H05K2201/09509 , H05K2201/09827 , H05K2203/0165 , H05K2203/095 , H05K3/0008 , H05K3/0055 , H05K3/4644
摘要： A method for producing holes in a polymer film includes the steps of irradiating a spot on the film with a burst of focused laser energy at a level sufficient to damage the film without puncturing it and then subsequently plasma etching the irradiated film so as to remove the damaged portions. This method is particularly applicable to the formation of multichip integrated circuit packages in which a plurality of microcircuit chips are affixed to an underlying substrate which is coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting the chips or making intrachip connections by means of a subsequently applied metallization layer.
摘要翻译：一种聚合物膜中的孔的制造方法，其特征在于，具有将聚焦的激光能量的突发以足以破坏所述膜的水平的方式照射在所述膜上的斑点的步骤，然后等离子体蚀刻所述被照射的膜，损坏部分。该方法特别适用于多芯片集成电路封装的形成，其中多个微电路芯片固定到涂覆有覆盖芯片和基板的聚合物膜的下面的基板上。提供这些孔用于通过随后应用的金属化层互连芯片或进行连接间连接的目的。

7. 发明授权

US4430557A Cooking apparatus having internal pressurizing source and _integral heat source _ 失效
标题翻译：具有内部加压源和整体热源的烹饪设备
公开(公告)号：US4430557A
公开(公告)日：1984-02-07
申请号：US336805
申请日：1982-01-04
申请人： Charles W. Eichelberger , Robert J. Wojnarowski , Thomas M. O'Loughlin
发明人： Charles W. Eichelberger , Robert J. Wojnarowski , Thomas M. O'Loughlin
IPC分类号： F24C7/04 , A47J27/00 , A47J27/16 , A47J37/06 , F27D11/02 , A21B1/00
CPC分类号： A47J27/16 , A47J37/0623 , A47J37/0629
摘要： A self-standing cooking apparatus is disclosed which consists of a pressurizable vessel having a door which can be latched and sealed, an integral steam-pressure source and integral upper and lower heating rod elements which serve as broil elements and bake elements, respectively, and a water-filled tray which can be disposed above the upper heating rod. An electrical control circuit enables selective energization of the bake and broil heat elements by continuous or controlled duration pulses of current which control the proportion of infrared energy that will be produced by the heating rods. The oven can be operated under pressure with the heating rods applying infrared radiation to the foodstuff being cooked in order to obtain browning or crisping of the foodstuff which is cooked at elevated pressure. The oven can also be operated in a conventional bake mode, a conventional broil mode, a steam cooking mode, a sealed cooking and warming mode and a toasting mode. Reinforcing fins lying in parallel planes are secured to and encircle the exterior of the container to provide necessary additional strength for the pressurizable vessel walls to withstand a maximum design pressure.
摘要翻译：公开了一种独立的烹饪设备，其包括具有可锁定和密封的门的可加压容器，分别用作烤肉元件和烘烤元件的整体蒸汽压力源和整体的上下加热棒元件，以及可以设置在上加热棒上方的充水托盘。电控制电路能够通过连续或受控持续的电流脉冲来选择性地激励烘烤和烘烤加热元件，从而控制由加热棒产生的红外能量的比例。烘箱可以在压力下操作，加热棒将红外辐射施加到烹饪的食品上，以获得在升高的压力下烹饪的食物的褐变或脆化。烘箱也可以以常规烘烤模式，常规烘烤模式，蒸汽烹饪模式，密封烹饪和加温模式以及烘烤模式操作。位于平行平面上的加强肋被固定在容器的外部并且环绕容器的外部，以便为可加压容器壁承受最大设计压力提供必要的附加强度。

8. 发明授权

US4404237A Fabrication of electrical conductor by replacement of metallic powder in polymer with more noble metal 失效
标题翻译：通过用更贵金属代替聚合物中的金属粉末来制造电导体
公开(公告)号：US4404237A
公开(公告)日：1983-09-13
申请号：US220342
申请日：1980-12-29
申请人： Charles W. Eichelberger , Robert J. Wojnarowski
发明人： Charles W. Eichelberger , Robert J. Wojnarowski
IPC分类号： H05K1/09 , H05K3/24 , H05K3/12 , H05K3/18
CPC分类号： H05K3/246 , H05K1/095
摘要： A low-cost conductor, e.g. a printed circuit, is prepared by applying a mixture of a metallic powder and polymer on a substrate and curing the polymer, followed by an augmentation replacement reaction being effected to replace some of the metallic powder with a more noble metal in such a way that the total volume of deposited metal on the surface exceeds that of the original metal powder at that surface. This procedure produces contiguous layer of conducting metal on the substrate. The conductors thus formed can easily be soldered without leaching using a conventional tin-lead solders.
摘要翻译：低成本导体，例如通过将金属粉末和聚合物的混合物施加到基底上并固化聚合物来制备印刷电路，然后进行增强置换反应以用更贵金属代替一些金属粉末，使得表面上沉积金属的总体积超过了该表面的原始金属粉末的总体积。该过程在衬底上产生连续的导电金属层。如此形成的导体可以容易地使用常规的锡铅焊料进行浸出而不进行浸出。

9. 发明授权

US5104480A Direct patterning of metals over a thermally inefficient surface using a laser 失效
标题翻译：使用激光直接绘制金属表面的热损伤表面
公开(公告)号：US5104480A
公开(公告)日：1992-04-14
申请号：US597255
申请日：1990-10-12
申请人： Robert J. Wojnarowski , Charles W. Eichelberger
发明人： Robert J. Wojnarowski , Charles W. Eichelberger
IPC分类号： B23K26/18 , B23K26/40 , H01C17/22 , H01C17/242 , H01L21/48 , H05K1/09 , H05K3/00 , H05K3/02 , H05K3/06 , H05K3/08 , H05K3/10 , H05K3/14 , H05K3/22 , H05K3/38
CPC分类号： H05K3/225 , B23K26/40 , H01C17/242 , H01L21/4846 , H05K3/027 , H05K3/062 , B23K2203/05 , B23K2203/08 , B23K2203/12 , B23K2203/14 , B23K2203/15 , B23K2203/16 , B23K2203/172 , B23K2203/26 , B23K2203/42 , B23K2203/50 , B23K2203/54 , H05K2201/0112 , H05K2201/0338 , H05K2201/2081 , H05K2203/0361 , H05K2203/0384 , H05K2203/173 , H05K2203/175 , H05K3/108 , H05K3/143 , H05K3/381 , H05K3/388
摘要： Conductive patterns may be formed on the surface of thermally inefficient substrates by depositing a uniform layer of metal thereover whose upper surface is substantially UV light absorbing followed by laser ablation of the deposited metal to leave the deposited metal only in the desired metal pattern. Thermally efficient substrates may be rendered thermally inefficient by the deposition of a thermally inefficient material thereon. That thermally inefficient material may be either electrically insulating or a metal. A two layer metallization comprising a first, thermally inefficient reactive metal and a second UV light absorbing metal is preferred. When disposed on a thermally inefficient substrate, this two layer metallization ablates reactively as the two layers burn off together. This laser ablation process substantially roughens the surface of polymer dielectrics and may be used to repair open traces in printed circuit structures.

10. 发明授权

US4937203A Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer 失效
标题翻译：使用可拆卸覆盖层测试电子电路和集成电路芯片的方法和配置
公开(公告)号：US4937203A
公开(公告)日：1990-06-26
申请号：US414895
申请日：1989-09-29
申请人： Charles W. Eichelberger , Robert J. Wojnarowski , Kenneth B. Welles, II
发明人： Charles W. Eichelberger , Robert J. Wojnarowski , Kenneth B. Welles, II
IPC分类号： G01R1/04 , G01R31/317 , H01L23/538
CPC分类号： G01R31/31723 , H01L23/5385 , H01L23/5387 , H01L23/5389 , G01R1/0408 , H01L2224/82039 , H01L2924/01014 , H01L2924/01322 , H01L2924/09701
摘要： The utilization of a removable overlay layer together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.
摘要翻译：使用可移除覆盖层及其相关联的金属化图案用于有效地为集成电路芯片提供晶片级整合。本发明的方法和结构提供了另外不可测试的系统的制造和测试。本发明还允许集成电路系统在速度和操作环境方面以其最终配置进行测试，并且本发明消除了与晶片或芯片探针相关的许多问题。本发明还使用临时或永久地固定在集成电路芯片封装中的专用测试芯片。

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