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1. 发明授权

US3932846A Electronic calculator having internal means for turning off display 失效
标题翻译：具有用于关闭显示器的内部装置的电子计算器
公开(公告)号：US3932846A
公开(公告)日：1976-01-13
申请号：US400438
申请日：1973-09-24
申请人： Charles W. Brixey , Glenn A. Hartsell , Jerry L. Vandierendonck
发明人： Charles W. Brixey , Glenn A. Hartsell , Jerry L. Vandierendonck
IPC分类号： G01R31/317 , G06F15/02 , G11C17/12 , G06F3/14
CPC分类号： G11C17/12 , G01R31/317 , G01R31/31721 , G06F15/0216
摘要： An electronic calculator system of the type having a keyboard input and a visual display is implemented in MOS/LSI semiconductor chips having a data memory, an arithmetic unit, a read-only-memory for storing instruction words, and control circuitry for operating the system in response to keyboard inputs by selecting addresses for instructions from the read-only-memory, all of which is located in monolithic semiconductor units. A technique is provided for turning off the display after a selected time period by holding an instruction word in an instruction register while repeatedly incrementing an address register for the ROM until it overflows, then branching to an address defined in such instruction word. This is repeated until the selected time period is reached.
摘要翻译：具有键盘输入和视觉显示的电子计算器系统在具有数据存储器，运算单元，用于存储指令字的只读存储器和用于操作系统的控制电路的MOS / LSI半导体芯片中实现响应于键盘输入，通过选择来自只读存储器的指令的地址，所有这些都位于单片半导体单元中。提供了一种技术，用于在选择的时间段内通过在指令寄存器中保持指令字而重复递增ROM的地址寄存器直到其溢出，然后分支到在该指令字中定义的地址，来关闭显示。直到达到所选择的时间段。

2. 发明授权

US3987416A Electronic calculator with display and keyboard scanning signal generator in data memory 失效
标题翻译：电子计算器，显示和键盘扫描信号发生器在数据存储器中
公开(公告)号：US3987416A
公开(公告)日：1976-10-19
申请号：US400437
申请日：1973-09-24
申请人： Jerry L. Vandierendonck , Roger J. Fisher , Glenn A. Hartsell
发明人： Jerry L. Vandierendonck , Roger J. Fisher , Glenn A. Hartsell
IPC分类号： G01R31/317 , G06F15/02 , G11C17/12 , G06F3/00
CPC分类号： G11C17/126 , G01R31/317 , G01R31/31721 , G06F15/02
摘要： An electronic calculator system of the type having a keyboard input and a visual display readout is implemented in MOS/LSI semiconductor chips having a data memory, an arithmetic unit, a read-only-memory for storing instruction words, and control circuitry for operating the system in response to keyboard inputs, all in monolithic semiconductor units. The keyboard and display are scanned by timing signals generated in the semiconductor unit by a register associated with the data memory.
摘要翻译：具有键盘输入和视觉显示读取的类型的电子计算器系统在具有数据存储器，运算单元，用于存储指令字的只读存储器的MOS / LSI半导体芯片中实现，以及用于操作系统响应于键盘输入，全部采用单片半导体单元。通过与数据存储器相关联的寄存器在半导体单元中产生的定时信号来扫描键盘和显示器。

3. 发明授权

US4200926A Electronic calculator implemented in semiconductor LSI chips with scanned keyboard and display 失效
标题翻译：电子计算器采用扫描键盘和显示器在半导体LSI芯片中实现
公开(公告)号：US4200926A
公开(公告)日：1980-04-29
申请号：US444226
申请日：1974-02-20
申请人： Michael J. Cochran , Jerry L. Vandierendonck
发明人： Michael J. Cochran , Jerry L. Vandierendonck
IPC分类号： C07D233/42 , G06F3/023 , G06F15/02 , H03M11/20 , G06F3/02 , G06F7/48
CPC分类号： H03M11/20 , C07D233/42 , G06F15/02 , G06F3/023
摘要： An electronic desk top calculator implemented in MOS/LSI technology and including a scanned keyboard input and display output. Data registers are provided in a sequentially addressed random access memory array, which is addressed by a commutator also used to generate encoded timing signals for other parts of the system and control logic. The keyboard input includes an interface register into which is entered key sense line information along with encoded timing information derived from the encoded timing signals. The contents of the interface register may be entered into the data registers or used to select an address in a program storage memory via a program counter. Bits may be read out in parallel from cells in the data registers and processed through an arithmetic logic unit and then re-entered in the same cells within a bit time or state time, so the data registers do not recirculate in the usual sense.
摘要翻译：电子桌面计算器采用MOS / LSI技术实现，包括扫描的键盘输入和显示输出。数据寄存器被提供在顺序寻址的随机存取存储器阵列中，其由换向器寻址，该换向器也用于为系统的其他部分和控制逻辑生成编码定时信号。键盘输入包括接口寄存器，其中输入了键传感线信息以及从经编码的定时信号导出的编码定时信息。接口寄存器的内容可以输入到数据寄存器中，或者用于通过程序计数器选择程序存储存储器中的地址。位可以从数据寄存器中的单元并行读出并通过算术逻辑单元进行读出，然后在位时间或状态时间内重新输入到相同的单元中，因此数据寄存器在通常的意义上不再循环。

4. 发明授权

US4225934A Multifunctional arithmetic and logic unit in semiconductor integrated circuit 失效
标题翻译：半导体集成电路中的多功能运算和逻辑单元
公开(公告)号：US4225934A
公开(公告)日：1980-09-30
申请号：US815871
申请日：1977-07-14
申请人： Jerry L. Vandierendonck
发明人： Jerry L. Vandierendonck
IPC分类号： G06F7/50 , G06F7/501 , G06F7/575 , G06F13/18
CPC分类号： G06F7/501 , G06F13/18 , G06F7/575 , G06F2207/3872
摘要： A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip. The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates.
摘要翻译：计算系统包括与外部存储器单元组合的中央处理器单元（CPU）。 CPU包括算术逻辑（ALU），指令寄存器，随机存取存储器和用于通过公共并行总线的顺序使用来互连CPU的功能元件的控制系统，使CPU能够在单个芯片上定义。 ALU能够使用公共逻辑门来执行八个独立的算术和逻辑功能。

5. 发明授权

US4037094A Multi-functional arithmetic and logical unit 失效
标题翻译：多功能算术和逻辑单元
公开(公告)号：US4037094A
公开(公告)日：1977-07-19
申请号：US176664
申请日：1971-08-31
申请人： Jerry L. Vandierendonck
发明人： Jerry L. Vandierendonck
IPC分类号： G06F7/50 , G06F7/501 , G06F7/575 , G06F13/18 , G06F7/48
CPC分类号： G06F7/501 , G06F13/18 , G06F7/575 , G06F2207/3872
摘要： A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip. The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates.
摘要翻译：计算系统包括与外部存储器单元组合的中央处理器单元（CPU）。 CPU包括算术逻辑（ALU），指令寄存器，随机存取存储器和用于通过公共并行总线的顺序使用来互连CPU的功能元件的控制系统，使CPU能够在单个芯片上定义。 ALU能够使用公共逻辑门来执行八个独立的算术和逻辑功能。

6. 发明授权

US3984816A Expandable function electronic calculator 失效
标题翻译：可扩展功能电子计算器
公开(公告)号：US3984816A
公开(公告)日：1976-10-05
申请号：US607525
申请日：1975-08-25
申请人： Michael J. Cochran , Jerry L. Vandierendonck
发明人： Michael J. Cochran , Jerry L. Vandierendonck
IPC分类号： G06F3/02
CPC分类号： G06F3/0227
摘要： An electronic portable calculator implemented in MOS/LSI technology and including a scanned keyboard input and display output. The calculator system utilizes a plurality of output terinals on the primary MOS/LSI chip for selectively addressing in timed coded sequence an array of peripheral MOS/LSI chips providing for expanded register and memory capacity and for output printing. Data registers are provided in a sequentially addressed random access memory array, which is addressed by a commutator also used to generate encoded timing signals for other parts of the system and control logic. The keyboard input includes an interface register into which is entered key sense line information along with encoded timing information derived from the encoded timing signals. The contents of the interface register may be entered into the data registers or used to select an address in a program storage memory via a program counter. Bits may be read out in parallel from cells in the data registers and processed through an arithmetic logic unit and then re-entered in the same cells within a bit time or state time, so the data registers do not recirculate in the usual sense.
摘要翻译：一种以MOS / LSI技术实现的电子便携式计算机，包括扫描的键盘输入和显示输出。计算器系统利用主MOS / LSI芯片上的多个输出端，以定时编码顺序有选择地寻址提供扩展寄存器和存储器容量并用于输出打印的外围MOS / LSI芯片阵列。数据寄存器被提供在顺序寻址的随机存取存储器阵列中，其由换向器寻址，该换向器也用于为系统的其他部分和控制逻辑生成编码定时信号。键盘输入包括接口寄存器，其中输入了键传感线信息以及从经编码的定时信号导出的编码定时信息。接口寄存器的内容可以输入到数据寄存器中，或者用于通过程序计数器选择程序存储存储器中的地址。位可以从数据寄存器中的单元并行读出并通过算术逻辑单元进行读出，然后在位时间或状态时间内重新输入到相同的单元中，因此数据寄存器在通常的意义上不再循环。

7. 发明授权

US4049974A Precharge arithmetic logic unit 失效
标题翻译：预充电算术逻辑单元
公开(公告)号：US4049974A
公开(公告)日：1977-09-20
申请号：US441917
申请日：1974-02-12
申请人： Gary W. Boone , Jerry L. Vandierendonck
发明人： Gary W. Boone , Jerry L. Vandierendonck
IPC分类号： G06F7/50 , G06F7/575 , G06F11/10 , G06F13/18 , G06F15/78 , H03K19/08
CPC分类号： G06F7/575 , G06F11/10 , G06F13/18 , G06F15/7896 , G06F7/501 , G06F2207/3872 , Y10S68/903
摘要： A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes, on a single chip, an arithmetic logic unit (ALU), an instruction register, a random access memory and a control system. Interconnection of the functional elements of the CPU is accomplished via sequential use of a common parallel buss. The ALU contains precharged parity and carry propagate circuits which enhance circuit speed. The precharged circuits are formed using conventional insulated-gate-field-effect transistor fabrication techniques.
摘要翻译：计算系统包括与外部存储器单元组合的中央处理器单元（CPU）。 CPU在单个芯片上包括算术逻辑单元（ALU），指令寄存器，随机存取存储器和控制系统。 CPU的功能元件的互连通过公共并联总线的顺序使用来实现。 ALU包含预充电奇偶校验和携带增强电路速度的传播电路。预充电电路使用传统的绝缘栅场效应晶体管制造技术形成。

8. 发明授权

US4503511A Computing system with multifunctional arithmetic logic unit in single integrated circuit 失效
标题翻译：单一集成电路中具有多功能运算逻辑单元的计算系统
公开(公告)号：US4503511A
公开(公告)日：1985-03-05
申请号：US397720
申请日：1982-07-13
申请人： Jerry L. Vandierendonck
发明人： Jerry L. Vandierendonck
IPC分类号： G06F7/50 , G06F7/501 , G06F13/18
CPC分类号： G06F7/501 , G06F13/18 , G06F2207/3872
摘要： A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip. The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates.
摘要翻译：计算系统包括与外部存储器单元组合的中央处理器单元（CPU）。 CPU包括算术逻辑（ALU），指令寄存器，随机存取存储器和用于通过公共并行总线的顺序使用来互连CPU的功能元件的控制系统，使CPU能够在单个芯片上定义。 ALU能够使用公共逻辑门来执行八个独立的算术和逻辑功能。

9. 发明授权

US4004280A Calculator data storage system 失效
标题翻译：计算器数据存储系统
公开(公告)号：US4004280A
公开(公告)日：1977-01-18
申请号：US593594
申请日：1975-07-07
申请人： Jerry L. Vandierendonck
发明人： Jerry L. Vandierendonck
IPC分类号： G06F9/30 , G06F13/42 , G06F15/78 , G06F13/00
CPC分类号： G06F9/30141 , G06F13/4243 , G06F15/7864 , G06F9/30138
摘要： Disclosed is an expandable calculator system of the type implemented on semiconductor chips providing additional data storage registers for increasing data storage capacity of the basic system. A basic calculator system comprising two semiconductor chips is provided with additional semiconductor chips each providing a plurality of separately addressable registers for storing data, to thereby increase the data storage capacity of the two-chip system. First and second control signals synchronize the internal timing of the external register chips and also enable communication to the external chips. The data system has 10 registers on each of the additional semiconductor chips which are addressed by means responsive to instructions communicated via the data transmission path.
摘要翻译：公开了一种在半导体芯片上实现的可扩展计算器系统，其提供用于增加基本系统的数据存储容量的附加数据存储寄存器。包括两个半导体芯片的基本计算器系统设置有附加的半导体芯片，每个半导体芯片提供多个用于存储数据的单独可寻址的寄存器，从而增加双芯片系统的数据存储容量。第一和第二控制信号同步外部寄存器芯片的内部定时，并且还能够与外部芯片通信。数据系统在每个附加半导体芯片上具有10个寄存器，这些寄存器通过响应于经由数据传输路径传送的指令的方式寻址。

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