专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07861022B2 Livelock resolution 有权
标题翻译： Livelock分辨率
公开(公告)号：US07861022B2
公开(公告)日：2010-12-28
申请号：US12393469
申请日：2009-02-26
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F13/36 , G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F11/362 , G06F11/0724 , G06F11/0757
摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译：提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。控制处理器执行动作以尝试解决动态锁定状态。一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

2. 发明申请

US20080071955A1 Livelock Resolution Method and Apparatus 有权
标题翻译： Livelock分辨率方法和装置
公开(公告)号：US20080071955A1
公开(公告)日：2008-03-20
申请号：US11532987
申请日：2006-09-19
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F13/36
CPC分类号： G06F11/362 , G06F11/0724 , G06F11/0757
摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译：提供了用于解决多处理器数据处理系统中的活锁状态的机制。当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。控制处理器执行动作以尝试解决动态锁定状态。一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

3. 发明授权

US08171448B2 Structure for a livelock resolution circuit 有权
标题翻译：活动锁分辨率电路的结构
公开(公告)号：US08171448B2
公开(公告)日：2012-05-01
申请号：US12129777
申请日：2008-05-30
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F17/50
CPC分类号： G06F11/0757
摘要： A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译：提供了一种用于动态锁分辨率电路的设计结构。当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。控制处理器执行动作以尝试解决动态锁定状态。一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。另一方面，如果控制处理器确定预定量的时间没有进行任何进展，则确定已经发生了挂起状况。

4. 发明申请

US20090164682A1 Livelock Resolution 有权
标题翻译： Livelock分辨率
公开(公告)号：US20090164682A1
公开(公告)日：2009-06-25
申请号：US12393469
申请日：2009-02-26
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F12/00
CPC分类号： G06F11/362 , G06F11/0724 , G06F11/0757
摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译：提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。控制处理器执行动作以尝试解决动态锁定状态。一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。另一方面，如果控制处理器确定预定量的时间没有进行任何进展，则确定已经发生了挂起状况。

5. 发明授权

US07500035B2 Livelock resolution method 有权
标题翻译： Livelock分辨率方法
公开(公告)号：US07500035B2
公开(公告)日：2009-03-03
申请号：US11532987
申请日：2006-09-19
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F13/36 , G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F11/362 , G06F11/0724 , G06F11/0757
摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译：提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。控制处理器执行动作以尝试解决动态锁定状态。一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

6. 发明申请

US20080228974A1 Design Structure for a Livelock Resolution Circuit 有权
标题翻译：固定锁分辨率电路的设计结构
公开(公告)号：US20080228974A1
公开(公告)日：2008-09-18
申请号：US12129777
申请日：2008-05-30
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F13/00
CPC分类号： G06F11/0757
摘要： A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译：提供了一种用于动态锁分辨率电路的设计结构。当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。控制处理器执行动作以尝试解决动态锁定状态。一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。

7. 发明申请

US20080065873A1 DYNAMIC LIVELOCK RESOLUTION WITH VARIABLE DELAY MEMORY ACCESS QUEUE 审中-公开
标题翻译：具有可变延迟记忆访问队列的动态生存解决方案
公开(公告)号：US20080065873A1
公开(公告)日：2008-03-13
申请号：US11530612
申请日：2006-09-11
申请人： Ronald Hall , Michael L. Karm , Alvan W. Ng , Todd A. Venton
发明人： Ronald Hall , Michael L. Karm , Alvan W. Ng , Todd A. Venton
IPC分类号： G06F9/44
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/3834 , G06F9/3867 , G06F12/0891
摘要： A method for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes. These processes include dynamically configuring the delay queue within the processor into one of two different configurations and changing the sequence and timing of handling memory access instructions, based on the specific configuration of the delay queue.
摘要翻译：一种用于解决处理器核心和存储器子系统控制器之间的接口处的活动锁定的发生的方法。通过在处理器内引入动态锁定检测机制（包括活动锁定检测实用程序或逻辑）来解决活锁，以检测活动锁定状态并动态地改变延迟阶段的持续时间，以便改变“谐波”固定循环回路行为。活动锁定检测逻辑（LDL）计算特定指令的刷新次数或指令重新发出而不完成的次数。然后，LDL将该数字与预设的阈值数进行比较。基于比较的结果，LDL触发了两种不同的动态锁定解析过程之一的实现。这些过程包括基于延迟队列的具体配置，将处理器内的延迟队列动态地配置为两种不同配置之一并且改变处理存储器访问指令的顺序和定时。

8. 发明授权

US4761730A Computer memory apparatus 失效
标题翻译：计算机存储装置
公开(公告)号：US4761730A
公开(公告)日：1988-08-02
申请号：US751179
申请日：1985-07-02
申请人： Alvan W. Ng , Edwin P. Fisher
发明人： Alvan W. Ng , Edwin P. Fisher
IPC分类号： G06F12/04 , G11C5/00 , G11C8/12 , G11C8/18 , G06F13/00
CPC分类号： G11C8/12 , G06F12/04 , G11C5/00 , G11C8/18
摘要： A memory subsystem couples to a bus in common with and proceses memory requests received therefrom. The subsystem includes a single addressable memory module unit or stack having a number of word blocks of dynamic random access memory (DRAM) chips mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. Chip select circuits preselect a pair of blocks of RAM chips from the stack. Timing circuits generate a plurality of sequential column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the sequential read out of a pair of words from the preselected blocks of the single word wide module into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out in sequence providing a double fetch capability without any loss in system performance.
摘要翻译：存储器子系统共同耦合到总线并处理从其接收的存储器请求。子系统包括单个可寻址存储器模块单元或堆叠，其具有安装在单个电路板上的动态随机存取存储器（DRAM）芯片的多个字块，其通过单个字宽的接口连接到子系统的其余部分。芯片选择电路从堆栈中预选一对RAM芯片块。定时电路产生多个顺序列地址脉冲，其被选择性地施加到由行地址脉冲定义的间隔内的预选芯片块。这导致从单个单词宽模块的预选块中顺序读出一对单词到一对子系统数据寄存器中。对于每个存储器读取请求，来自每个预先选择的块对中的字被顺序地读出，提供双重提取能力，而不会在系统性能上任何损失。

9. 发明授权

US08499124B2 Handling castout cache lines in a victim cache 失效
标题翻译：在受害者缓存中处理castout缓存行
公开(公告)号：US08499124B2
公开(公告)日：2013-07-30
申请号：US12336048
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0811 , G06F12/0862
摘要： A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller, responsive to receiving a castout command identifying a victim cache line castout from another cache memory, causes the victim cache line to be held in the cache array. If the other cache memory is a higher level cache in the cache hierarchy of the processor core, the cache controller marks the victim cache line in the cache directory so that it is less likely to be evicted by a replacement policy of the victim cache, and otherwise, marks the victim cache line in the cache directory so that it is more likely to be evicted by the replacement policy of the victim cache.
摘要翻译：受害者缓存存储器包括缓存阵列，高速缓存阵列的内容的高速缓存目录以及控制受害者缓存存储器的操作的高速缓存控制器。高速缓存控制器响应于从另一高速缓冲存储器接收识别受害者高速缓存线路突发的丢弃命令，使受害者高速缓存行保持在高速缓存阵列中。如果其他高速缓冲存储器是处理器核心的高速缓存层级中的较高级缓存，则高速缓存控制器将高速缓存目录中的受害者高速缓存行标记为不太可能被受害缓存的替换策略驱逐，否则，将缓存目录中的受害者缓存行标记为更有可能被受害者缓存的替换策略驱逐。

10. 发明申请

US20100235584A1 Lateral Castout (LCO) Of Victim Cache Line In Data-Invalid State 有权
标题翻译：受害者高速缓存行在数据无效状态下的横向延伸（LCO）
公开(公告)号：US20100235584A1
公开(公告)日：2010-09-16
申请号：US12402025
申请日：2009-03-11
申请人： Guy L. Guthrie , Hien M. Le , Alvan W. Ng , Michael S. Siegel , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Hien M. Le , Alvan W. Ng , Michael S. Siegel , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/12 , G06F12/128
摘要： A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.
摘要翻译：选择具有数据无效相干状态的受害者缓存线，用于从第一处理单元的第一较低级缓存进行舍入。第一处理单元在互连结构上发出用于标识要从第一较低级高速缓存丢弃的受害缓存行的横向聚合（LCO）命令，指示数据无效相干状态，并指示较低级别高速缓存是预期目的地的受害者缓存行。响应于指示LCO命令成功的LCO命令的一致性响应，从第一低级缓存中移除受害者高速缓存行并将其保存在数据无效一致状态中的第二处理单元的第二较低级高速缓存中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式