专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07385913B2 Method and apparatus for compensating for variations in a receive portion of a wireless communication device 有权
标题翻译：用于补偿无线通信设备的接收部分中的变化的方法和装置
公开(公告)号：US07385913B2
公开(公告)日：2008-06-10
申请号：US10131660
申请日：2002-04-24
申请人： Charles Leroy Sobchak , Mahibur Rahman , Clinton C Powell
发明人： Charles Leroy Sobchak , Mahibur Rahman , Clinton C Powell
IPC分类号： H04J11/00 , H04B7/216
CPC分类号： H04L25/03133 , H04L2025/0377
摘要： A generator (304) generates first and second training signals (320, 318) that originate within a wireless communication device (FIG. 3) instead of being received from a source outside the device. A receive portion (212, 214, 216) of the device processes the first training signal to derive a processed training signal. An adaptive equalizer (310) equalizes the processed training signal to derive an equalized training signal. A processor (312) compares the equalized training signal and the second training signal using an adaptive algorithm to derive coefficients for the adaptive equalizer to compensate for variations in the receive portion, and adjusts the adaptive equalizer in accordance with the coefficients to derive a compensated output signal.
摘要翻译：发生器（304）生成起始于无线通信设备（图3）的第一和第二训练信号（320,318），而不是从设备外部的源接收。设备的接收部分（212,214,216）处理第一训练信号以导出经处理的训练信号。自适应均衡器（310）对经处理的训练信号进行均衡以导出均衡的训练信号。处理器（312）使用自适应算法比较均衡的训练信号和第二训练信号，以导出自适应均衡器的系数以补偿接收部分的变化，并且根据系数调整自适应均衡器以导出补偿的输出信号。

2. 发明授权

US08238860B2 Tuning a second order intercept point of a mixer in a receiver 有权
标题翻译：调整接收机中混频器的二阶截取点
公开(公告)号：US08238860B2
公开(公告)日：2012-08-07
申请号：US12018354
申请日：2008-01-23
申请人： Charles LeRoy Sobchak , Mahibur Rahman , Manish N. Shah
发明人： Charles LeRoy Sobchak , Mahibur Rahman , Manish N. Shah
IPC分类号： H04B17/00
CPC分类号： H04B1/30
摘要： An IP2 tuning circuit (404, 1004, 1104 and 1404) for tuning the IP2 of a mixer (414 and 415) to minimize second order intermodulation distortion (IMD2) in a receiver (402, 1002, 1102 and 1402) of a transceiver (401, 1001, 1101 and 1401). An operating characteristic of the mixer related to IMD2 is changeable by changing a value of a setting of the mixer. Two tones outside a bandpass of the receiver are injected into the mixer and a calibration tone within the bandpass is produced as a result of IMD2. Alternatively, a DSSS signal is injected into the mixer and the calibration tone is produced at a chip rate of the DSSS signal. The power of the calibration tone is measured at a plurality of values of the settings. Alternatively, a four-level PN DSSS signal of known content is injected into the mixer, and a two-level PN DSSS signal of known content produced therefrom is correlated with a two-level PN DSSS signal of known content produced by a squaring circuit (1468).
摘要翻译： IP2调谐电路（404,1004,1104和1404），用于调谐混频器（414和415）的IP2，以使收发器的接收器（402,1002,1102和1402）中的二阶互调失真（IMD2）最小化 401,1001,1101和1401）。与IMD2相关的混频器的工作特性可以通过改变混频器的设置值来改变。接收机带通外的两个音调被注入到混频器中，并且作为IMD2的结果产生带通内的校准音。或者，将DSSS信号注入到混频器中，并以DSSS信号的码片速率产生校准音。在多个设定值下测量校准音的功率。或者，已知内容的四电平PN DSSS信号被注入到混频器中，并且由其生成的已知内容的两级PN DSSS信号与由平方电路产生的已知内容的两电平PN DSSS信号相关 1468）。

3. 发明授权

US08165255B2 Multirate resampling and filtering system and method 有权
标题翻译：多速率重采样和滤波系统及方法
公开(公告)号：US08165255B2
公开(公告)日：2012-04-24
申请号：US12339787
申请日：2008-12-19
申请人： Charles LeRoy Sobchak , Mahibur Rahman
发明人： Charles LeRoy Sobchak , Mahibur Rahman
IPC分类号： H04L7/00
CPC分类号： H03H17/0685
摘要： A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module stores fewer samples than the number of samples between samples to be removed. A coefficient generator (240) in the resampling circuit generates a sequence of finite impulse response filter coefficients, with each coefficient in the sequence being associated with a respective distinct portion of a plurality of discrete time signal samples. A coefficient multiplier (264) multiplies each of the sequential plurality of finite impulse response filter coefficients by its associated respective distinct portion of the plurality of discrete time signal samples. An adder (236) produces a resampled output sample that consists of a sum of elements of the product vector produced by the coefficient multiplier.
摘要翻译：离散时间信号重采样电路（200）。数据样本处理模块（260）从连续多个离散时间信号样本中移除所选择的样本，以实现分数重采样，其中数据样本处理模块存储的样本少于要移除样本数的样本数。重采样电路中的系数发生器（240）产生有序脉冲响应滤波器系数序列，序列中的每个系数与多个离散时间信号采样的相应不同部分相关联。系数乘法器（264）将连续多个有限脉冲响应滤波器系数中的每一个乘以多个离散时间信号样本的相关联的不同部分。加法器（236）产生由系数乘法器产生的乘积矢量的元素之和组成的重采样输出样本。

4. 发明授权

US07760816B2 Automatic gain control using multiple equalized estimates dynamic hysteresis 失效
标题翻译：自动增益控制采用多重均衡估计动态滞后
公开(公告)号：US07760816B2
公开(公告)日：2010-07-20
申请号：US11622402
申请日：2007-01-11
申请人： Charles LeRoy Sobchak , Mahibur Rahman , Lynn R. Freytag
发明人： Charles LeRoy Sobchak , Mahibur Rahman , Lynn R. Freytag
IPC分类号： H04K1/02 , H04L27/06 , H04B1/06 , H04B7/00
CPC分类号： H04L27/01 , H03G3/3057
摘要： At least one adjustable gain analog amplifier (120, 124 and 128) in an analog line-up (102) amplifies by a gain an analog signal at an input of the analog line-up (102). The at least one adjustable gain analog amplifier (120, 124 and 128) is operable at one or more gains. At least one digital estimation device (134, 140 and 146) receives signal via an output (108) of the analog line-up (10) and provides a digital signal estimate representative of an analog signal at an input of a respective one of the at least one adjustable gain analog amplifier (120, 124 and 128) in the analog line-up (102). An AGC controller (152) monitors the digital signal estimate. The AGC controller (152) adjusts the gain of the at least one analog amplifier (120, 124 and 128). An RF receiver and an integrated circuit utilizing the novel features are also disclosed.
摘要翻译：模拟阵容（102）中的至少一个可调增益模拟放大器（120,124和128）通过在模拟阵容（102）的输入处的模拟信号的增益来放大。所述至少一个可调增益模拟放大器（120,124和128）可在一个或多个增益下操作。至少一个数字估计装置（134,140和146）经由模拟阵容（102）的输出（108）接收信号，并且提供代表模拟信号的模拟信号的数字信号估计模拟阵列（102）中的至少一个可调增益模拟放大器（120,124和128）。 AGC控制器（152）监视数字信号估计。 AGC控制器（152）调节至少一个模拟放大器（120,124和128）的增益。还公开了RF接收机和利用新颖特征的集成电路。

5. 发明授权

US07912437B2 Radio frequency receiver having dynamic bandwidth control and method of operation 有权
标题翻译：具有动态带宽控制和操作方法的射频接收机
公开(公告)号：US07912437B2
公开(公告)日：2011-03-22
申请号：US11621355
申请日：2007-01-09
申请人： Mahibur Rahman , Charles LeRoy Sobchak
发明人： Mahibur Rahman , Charles LeRoy Sobchak
IPC分类号： H04B1/10
CPC分类号： H04B1/30 , H04L27/0002 , H04L27/22
摘要： A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.
摘要翻译：射频接收器（102）包括用于放大由射频接收机接收的信号的至少一个放大器（108,114和122），用于控制至少一个放大器的增益的自动增益控制系统（158），以及用于减少由至少一个放大器放大的信号的任何直流分量的直流偏移校正滤波器（142）。直流偏移校正滤波器具有由至少一个放大器的增益的变化动态地控制的带宽。无线电频率接收机还包括一个数字自动增益控制单元（150），该数字自动增益控制单元具有由至少一个放大器的增益变化动态控制的带宽。

6. 发明申请

US20090186587A1 TUNING A SECOND ORDER INTERCEPT POINT OF A MIXER IN A RECEIVER 有权
标题翻译：调整接收器中混合器的第二个订单中间点
公开(公告)号：US20090186587A1
公开(公告)日：2009-07-23
申请号：US12018354
申请日：2008-01-23
申请人： CHARLES LEROY SOBCHAK , Mahibur Rahman , Manish N. Shah
发明人： CHARLES LEROY SOBCHAK , Mahibur Rahman , Manish N. Shah
IPC分类号： H04B1/26
CPC分类号： H04B1/30
摘要： An IP2 tuning circuit (404, 1004, 1104 and 1404) for tuning the IP2 of a mixer (414 and 415) to minimize second order intermodulation distortion (IMD2) in a receiver (402, 1002, 1102 and 1402) of a transceiver (401, 1001, 1101 and 1401). An operating characteristic of the mixer related to IMD2 is changeable by changing a value of a setting of the mixer. Two tones outside a bandpass of the receiver are injected into the mixer and a calibration tone within the bandpass is produced as a result of IMD2. Alternatively, a DSSS signal is injected into the mixer and the calibration tone is produced at a chip rate of the DSSS signal. The power of the calibration tone is measured at a plurality of values of the settings. Alternatively, a four-level PN DSSS signal of known content is injected into the mixer, and a two-level PN DSSS signal of known content produced therefrom is correlated with a two-level PN DSSS signal of known content produced by a squaring circuit (1468).
摘要翻译： IP2调谐电路（404,1004,1104和1404），用于调谐混频器（414和415）的IP2，以使收发器的接收器（402,1002,1102和1402）中的二阶互调失真（IMD2）最小化 401,1001,1101和1401）。与IMD2相关的混频器的工作特性可以通过改变混频器的设置值而改变。接收机带通外的两个音调被注入到混频器中，并且作为IMD2的结果产生带通内的校准音。或者，将DSSS信号注入到混频器中，并以DSSS信号的码片速率产生校准音。在多个设定值下测量校准音的功率。或者，已知内容的四电平PN DSSS信号被注入到混频器中，并且由其生成的已知内容的两级PN DSSS信号与由平方电路产生的已知内容的两电平PN DSSS信号相关 1468）。

7. 发明授权

US07782991B2 Fractionally related multirate signal processor and method 有权
标题翻译：分数相关的多速率信号处理器和方法
公开(公告)号：US07782991B2
公开(公告)日：2010-08-24
申请号：US11621387
申请日：2007-01-09
申请人： Charles LeRoy Sobchak , Mahibur Rahman , Emilio J. Quiroga
发明人： Charles LeRoy Sobchak , Mahibur Rahman , Emilio J. Quiroga
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H04L7/0029 , H03H17/0628 , H03H17/0685
摘要： A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.
摘要翻译：一种具有重采样滤波器（106）的多速率处理电路（100），用于接受以第一时钟速率采样的采样输入信号（104），并且对采样的输入信号进行滤波以去除高于第二时钟速率的频谱带宽的频谱分量。采样的输入信号表示以与第一时钟速率有关的第二时钟速率更有效地处理的信号。多速率处理电路（100）还具有离散时间处理器（108），其接收重采样滤波器输出（130）并且处理以第一时钟速率的两倍的整数倍的输出。离散时间处理器（108）还进一步从处理中排除所选择的采样，以便以第二时钟速率的两倍的整数倍有效地执行重采样滤波器输出（130）的离散时间处理。

8. 发明申请

US20080165907A1 FRACTIONALLY RELATED MULTIRATE SIGNAL PROCESSOR AND METHOD 有权
标题翻译：相关的多相信号处理器和方法
公开(公告)号：US20080165907A1
公开(公告)日：2008-07-10
申请号：US11621387
申请日：2007-01-09
申请人： Charles LeRoy SOBCHAK , Mahibur Rahman , Emilio J. Quiroga
发明人： Charles LeRoy SOBCHAK , Mahibur Rahman , Emilio J. Quiroga
IPC分类号： H04L7/00
CPC分类号： H04L7/0029 , H03H17/0628 , H03H17/0685
摘要： A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.
摘要翻译：一种具有重采样滤波器（106）的多速率处理电路（100），用于接受以第一时钟速率采样的采样输入信号（104），并且对采样的输入信号进行滤波以去除高于第二时钟速率的频谱带宽的频谱分量。采样的输入信号表示以与第一时钟速率有关的第二时钟速率更有效地处理的信号。多速率处理电路（100）还具有离散时间处理器（108），其接收重采样滤波器输出（130）并且处理以第一时钟速率的两倍的整数倍的输出。离散时间处理器（108）还进一步从处理中排除所选择的采样，以便以第二时钟速率的两倍的整数倍有效地执行重采样滤波器输出（130）的离散时间处理。

9. 发明申请

US20080165899A1 RADIO FREQUENCY RECEIVER HAVING DYNAMIC BANDWIDTH CONTROL AND METHOD OF OPERATION 有权
标题翻译：具有动态带宽控制的无线电频率接收机和操作方法
公开(公告)号：US20080165899A1
公开(公告)日：2008-07-10
申请号：US11621355
申请日：2007-01-09
申请人： Mahibur Rahman , Charles LeRoy Sobchak
发明人： Mahibur Rahman , Charles LeRoy Sobchak
IPC分类号： H04L27/08 , H04B1/16
CPC分类号： H04B1/30 , H04L27/0002 , H04L27/22
摘要： A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.
摘要翻译：射频接收器（102）包括用于放大由射频接收机接收的信号的至少一个放大器（108,114和122），用于控制至少一个放大器的增益的自动增益控制系统（158），以及用于减少由至少一个放大器放大的信号的任何直流分量的直流偏移校正滤波器（142）。直流偏移校正滤波器具有由至少一个放大器的增益的变化动态地控制的带宽。无线电频率接收机还包括一个数字自动增益控制单元（150），该数字自动增益控制单元具有由至少一个放大器的增益变化动态控制的带宽。

10. 发明申请

US20100158178A1 MULTIRATE RESAMPLING AND FILTERING SYSTEM AND METHOD 有权
标题翻译： MULTIRATE RESAMPLING和FILTERING系统和方法
公开(公告)号：US20100158178A1
公开(公告)日：2010-06-24
申请号：US12339787
申请日：2008-12-19
申请人： CHARLES LEROY SOBCHAK , Mahibur Rahman
发明人： CHARLES LEROY SOBCHAK , Mahibur Rahman
IPC分类号： H04L7/00
CPC分类号： H03H17/0685
摘要： A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module stores fewer samples than the number of samples between samples to be removed. A coefficient generator (240) in the resampling circuit generates a sequence of finite impulse response filter coefficients, with each coefficient in the sequence being associated with a respective distinct portion of a plurality of discrete time signal samples. A coefficient multiplier (264) multiplies each of the sequential plurality of finite impulse response filter coefficients by its associated respective distinct portion of the plurality of discrete time signal samples. An adder (236) produces a resampled output sample that consists of a sum of elements of the product vector produced by the coefficient multiplier.
摘要翻译：离散时间信号重采样电路（200）。数据样本处理模块（260）从连续多个离散时间信号样本中移除所选择的样本，以实现分数重采样，其中数据样本处理模块存储的样本少于要移除样本数的样本数。重采样电路中的系数发生器（240）产生有序脉冲响应滤波器系数序列，序列中的每个系数与多个离散时间信号采样的相应不同部分相关联。系数乘法器（264）将连续多个有限脉冲响应滤波器系数中的每一个乘以多个离散时间信号样本的相关联的不同部分。加法器（236）产生由系数乘法器产生的乘积矢量的元素之和组成的重采样输出样本。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式