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1. 发明申请

US20080132065A1 METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：在集成电路设计中从VIAS重新排列无声扩散的方法
公开(公告)号：US20080132065A1
公开(公告)日：2008-06-05
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

2. 发明授权

US06338992B1 Programmable read only memory in CMOS process flow 有权
公开(公告)号：US06338992B1
公开(公告)日：2002-01-15
申请号：US09726107
申请日：2000-11-29
申请人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
发明人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
IPC分类号： H01L218238
CPC分类号： H01L27/112 , H01L21/8238
摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices. Fuses are formed in associated with a portion of the nonvolatile memory devices to form read only memory devices of the fused portion of the nonvolatile memory devices.

3. 发明授权

US07582566B2 Method for redirecting void diffusion away from vias in an integrated circuit design 失效
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法
公开(公告)号：US07582566B2
公开(公告)日：2009-09-01
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

4. 发明授权

US06495881B1 Programmable read only memory in CMOS process flow 有权
公开(公告)号：US06495881B1
公开(公告)日：2002-12-17
申请号：US10012835
申请日：2001-10-22
申请人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
发明人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
IPC分类号： H01L29788
CPC分类号： H01L27/112 , H01L21/8238
摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices. Fuses are formed in associated with a portion of the nonvolatile memory devices to form read only memory devices of the fused portion of the nonvolatile memory devices.

5. 发明授权

US07436040B2 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US07436040B2
公开(公告)日：2008-10-14
申请号：US11323398
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

6. 发明授权

US07361965B2 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US07361965B2
公开(公告)日：2008-04-22
申请号：US11323400
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

7. 发明授权

US06967177B1 Temperature control system 有权
公开(公告)号：US06967177B1
公开(公告)日：2005-11-22
申请号：US09670975
申请日：2000-09-27
申请人： Charles E. May , Hemanshu D. Bhatt
发明人： Charles E. May , Hemanshu D. Bhatt
IPC分类号： B05C11/00 , C23C16/00 , C23F1/00 , H01L21/00 , H01L21/26 , H01L21/306 , H01L21/324 , H01L21/42 , H01L21/477
CPC分类号： H01L21/67248 , H01L21/67109
摘要： An apparatus for controlling the substrate temperature of a substrate during processing of the substrate at a process energy. A chuck temperature input receives temperature measurements from temperature sensors at a substrate chuck, and a temperature set point input receives temperature set points. The temperature set points define a range of temperatures within which the apparatus maintains the substrate temperature. A chuck temperature controller output sends control signals to a chuck temperature controller, which signals are operable to selectively increase and decrease the chuck temperature. A process energy output sends control signals that are operable to selectively increase and decrease the process energy during the processing of the substrate. A controller compares the temperature measurements received from the temperature sensors at the substrate chuck through the chuck temperature input to the temperature set points received through the temperature set point input. The controller sends control signals through the chuck temperature controller output to the chuck temperature controller to selectively decrease the chuck temperature when the temperature measurements received from the temperature sensors at the substrate chuck are above the temperature set points. The controller further sends control signals through the process energy output to selectively decrease the process energy when the temperature measurements received from the temperature sensors at the substrate chuck are above the temperature set point. Preferably, the controller first sends control signals through the chuck temperature controller output to control the chuck temperature, and only sends control signals through the process energy output when the chuck temperature cannot be sufficiently controlled by the chuck temperature controller.

8. 发明授权

US06482075B1 Process for planarizing an isolation structure in a substrate 有权
标题翻译：用于平坦化衬底中的隔离结构的方法
公开(公告)号：US06482075B1
公开(公告)日：2002-11-19
申请号：US09670998
申请日：2000-09-27
申请人： Hemanshu D. Bhatt , Shafqat Ahmed , Robindranath Banerjee , Charles E. May
发明人： Hemanshu D. Bhatt , Shafqat Ahmed , Robindranath Banerjee , Charles E. May
IPC分类号： B24B100
CPC分类号： H01L21/76232 , H01L21/76229
摘要： A process is described for planarizing an isolation structure in a substrate. The process includes depositing a pad protective material over an upper surface of the substrate, and selectively removing portions of the pad protective material to expose portions of the substrate and to form sidewalls in the pad protective material. A trench is formed in the exposed portions of the substrate, and a trench fill material is deposited in the trench and over the pad protective material. A trench protective material is deposited over the trench fill material and in contact with the sidewalls of the pad protective material, such that the pad protective material and portions of the trench protective material together form a continuous protective material layer. Portions of the trench protective material and the trench fill material are selectively removed down to the level of the upper surface of the pad protective material. Finally, the pad protective material and any remaining trench protective material is removed, leaving the trench filled with trench fill material that is planarized at the upper surface of the substrate. By forming a continuous protective material layer that completely covers the trench fill material in the trench, that material is protected during later process steps that nonselectively remove trench fill material lying outside the trench. In this manner, the trench fill material lying outside the trench may be removed without photolithographic masking and patterning steps. Thus, the process according to the invention reduces the cost and complexity of planarizing the trench fill material.
摘要翻译：描述了用于平坦化衬底中的隔离结构的过程。该方法包括在衬底的上表面上沉积衬垫保护材料，以及选择性地去除衬垫保护材料的部分以暴露衬底的部分并在衬垫保护材料中形成侧壁。在衬底的暴露部分中形成沟槽，并且沟槽填充材料沉积在沟槽中并在衬垫保护材料上方。沟槽保护材料沉积在沟槽填充材料上并与衬垫保护材料的侧壁接触，使得衬垫保护材料和沟槽保护材料的一部分一起形成连续的保护材料层。选择性地将沟槽保护材料和沟槽填充材料的部分向下移动到焊盘保护材料的上表面的高度。最后，去除衬垫保护材料和任何剩余的沟槽保护材料，留下填充沟槽填充材料的沟槽，其在衬底的上表面处被平坦化。通过形成完全覆盖沟槽中的沟槽填充材料的连续保护材料层，该材料在后续工艺步骤期间受到保护，非选择性地去除位于沟槽外部的沟槽填充材料。以这种方式，可以在没有光刻掩模和图案化步骤的情况下去除位于沟槽外部的沟槽填充材料。因此，根据本发明的方法降低了沟槽填充材料的平面化的成本和复杂性。

9. 发明授权

US06566244B1 Process for improving mechanical strength of layers of low k dielectric material 有权
标题翻译：用于提高低k介电材料层的机械强度的方法
公开(公告)号：US06566244B1
公开(公告)日：2003-05-20
申请号：US10138609
申请日：2002-05-03
申请人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
发明人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
IPC分类号： H01L214763
CPC分类号： H01L23/562 , H01L21/76801 , H01L21/76829 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.
摘要翻译：一种用于选择性地增强低k介电材料的部分的方法，其包括首先形成低k电介质层，然后在需要加强的低k层的部分中在低k层中形成开口，然后用增强材料填充开口，优选地具有比低k介电材料更高的杨氏弹性模量的增强材料。低k电介质材料的某些部分的这种选择性增强可以包括用增强材料选择性地增强接合焊盘下面的低k电介质材料。低k电介质材料可以通过在低k电介质层的下部形成的低k电介质材料中的开口加强，其中覆盖层将形成在低k电介质材料上。覆盖层的随后的形成将同时用封盖材料填充开口，该封盖材料然后也可以用作开口中的增强材料。

10. 发明授权

US06362510B1 Semiconductor topography having improved active device isolation and reduced dopant migration 有权
标题翻译：半导体形貌具有改进的有源器件隔离和减少掺杂剂迁移
公开(公告)号：US06362510B1
公开(公告)日：2002-03-26
申请号：US09206550
申请日：1998-12-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/2822 , H01L21/762 , H01L29/1083 , H01L29/36 , H01L29/518 , H01L29/6659 , H01L29/66651
摘要： A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.
摘要翻译：提出一种用于制造集成电路的方法，其中提供了在其上表面上形成有电介质层的半导体衬底。在从半导体衬底的上表面延伸到电介质层的上表面的电介质层中形成凹槽。然后在沟槽内生长硅外延层。阻挡原子与外延生长工艺同时并入硅外延层。

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