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1. 发明授权

US08836904B2 Liquid crystal display panel having a first conductive wire comprising at least two conductive portions having a resistivity that exceeds that of at least two isolated second connecting portions of the first conductive wire 有权
标题翻译：液晶显示面板具有第一导线，其包括至少两个导电部分，其电阻率超过第一导线的至少两个隔离的第二连接部分的电阻率
公开(公告)号：US08836904B2
公开(公告)日：2014-09-16
申请号：US12617878
申请日：2009-11-13
申请人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh , Chien-Ting Lai
发明人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh , Chien-Ting Lai
IPC分类号： G02F1/1343 , C09K19/52
CPC分类号： H05F3/00 , G02F1/1303 , G02F1/133345 , G02F1/134336 , G02F1/13439 , G02F1/1345 , G02F1/13452 , G02F2202/22
摘要： An exemplary liquid crystal display panel includes a substrate and first conductive wires. The first conductive wires are arranged at a surface of the substrate. Each of the first conductive wires includes a plurality of first connecting portions, a plurality of second connecting portions and a conductive portion with a plurality of conductive particles. The conductive portion is sandwiched between the first connecting portions and the second connecting portions, thus electrically connecting the first connecting portions to the second connecting portions. A method for manufacturing the liquid crystal display panel is also provided.
摘要翻译：示例性液晶显示面板包括基板和第一导线。第一导线布置在基板的表面。每个第一导线包括多个第一连接部分，多个第二连接部分和具有多个导电粒子的导电部分。导电部分夹在第一连接部分和第二连接部分之间，从而将第一连接部分电连接到第二连接部分。还提供了一种用于制造液晶显示面板的方法。

2. 发明授权

US08178878B2 Mother thin film transistor array substrate and thin film transistor array substrate fabricated therefrom 有权
标题翻译：母材薄膜晶体管阵列基板和由其制成的薄膜晶体管阵列基板
公开(公告)号：US08178878B2
公开(公告)日：2012-05-15
申请号：US12455823
申请日：2009-06-08
申请人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh
发明人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh
IPC分类号： H01L29/04
CPC分类号： G02F1/1345 , G02F1/133351 , H01L27/124 , H01L27/1285 , H01L27/1292
摘要： A mother thin film transistor (TFT) array substrate includes an insulating substrate, at least two TFT arrays and printed wirings. The TFT array includes TFTs formed on the insulating substrate. The printed wirings are connected to the TFT arrays. The printed wiring includes a discontinuous metal layer and at least one bridge layer connecting the discontinuous metal layer. The bridge layer is made from corrosion-resistant material.
摘要翻译：母体薄膜晶体管（TFT）阵列基板包括绝缘基板，至少两个TFT阵列和印刷布线。 TFT阵列包括形成在绝缘基板上的TFT。印刷的布线连接到TFT阵列。印刷布线包括不连续金属层和连接不连续金属层的至少一个桥接层。桥梁层由耐腐蚀材料制成。

3. 发明申请

US20100308331A1 Mother thin film transistor array substrate and thin film transistor array substrate fabricated therefrom 有权
标题翻译：母材薄膜晶体管阵列基板和由其制成的薄膜晶体管阵列基板
公开(公告)号：US20100308331A1
公开(公告)日：2010-12-09
申请号：US12455823
申请日：2009-06-08
申请人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh
发明人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh
IPC分类号： H01L29/04
CPC分类号： G02F1/1345 , G02F1/133351 , H01L27/124 , H01L27/1285 , H01L27/1292
摘要： A mother thin film transistor (TFT) array substrate includes an insulating substrate, at least two TFT arrays and printed wirings. The TFT array includes TFTs formed on the insulating substrate. The printed wirings are connected to the TFT arrays. The printed wiring includes a discontinuous metal layer and at least one bridge layer connecting the discontinuous metal layer. The bridge layer is made from corrosion-resistant material.
摘要翻译：母体薄膜晶体管（TFT）阵列基板包括绝缘基板，至少两个TFT阵列和印刷布线。 TFT阵列包括形成在绝缘基板上的TFT。印刷的布线连接到TFT阵列。印刷布线包括不连续金属层和连接不连续金属层的至少一个桥接层。桥梁层由耐腐蚀材料制成。

4. 发明授权

US08570478B2 Liquid crystal display panel and manufacturing method thereof 有权
公开(公告)号：US08570478B2
公开(公告)日：2013-10-29
申请号：US12788303
申请日：2010-05-27
申请人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh , Hung-Sheng Cho
发明人： Charles Chien , Shang-Yu Huang , Tsau-Hua Hsieh , Hung-Sheng Cho
IPC分类号： G02F1/1345
CPC分类号： G02F1/133784 , G02F1/133308 , G02F1/133345 , G02F1/13439 , G02F1/13452 , G02F1/13454 , G02F1/136286 , G02F1/1368 , G02F2001/13629 , G02F2203/28 , H01L27/124 , H01L33/08
摘要： A liquid crystal display panel includes a substrate, a thin film transistor array, a circuit, and a dummy circuit. One surface of the substrate is divided into a display region and a wiring region. The thin film transistor array is formed on the display region. The circuit and the dummy circuit are formed on the wiring region, the dummy circuit is adjacent to the circuit, and the circuit and the dummy circuit protrude from the substrate.

5. 发明授权

US07860470B2 Cross coupled high frequency buffer 有权
标题翻译：交叉耦合高频缓冲器
公开(公告)号：US07860470B2
公开(公告)日：2010-12-28
申请号：US11781198
申请日：2007-07-20
申请人： Zhiwei Xu , Heng-Yu Jian , Yi-Cheng Wu , Charles Chien
发明人： Zhiwei Xu , Heng-Yu Jian , Yi-Cheng Wu , Charles Chien
IPC分类号： H03J7/32
CPC分类号： H04B1/30 , H03F3/245 , H03F3/45183 , H03F3/45237 , H03F2203/45631 , H03F2203/45638
摘要： A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.
摘要翻译：本地振荡器（LO）缓冲电路包括以交叉耦合配置布置的第一和第二LO缓冲器。第一LO缓冲器响应于同相输入信号和来自第二LO缓冲器的正交输出信号产生同相输出信号。第二LO缓冲器响应于正交输入信号和同相输出信号产生正交输出信号。 LO缓冲器可以包括感性负载。 LO缓冲器可以包括MOS晶体管或双极结型晶体管。

6. 发明授权

US07609122B2 Method and system for calibration of a tank circuit in a phase lock loop 有权
标题翻译：在锁相环中调节电路的方法和系统
公开(公告)号：US07609122B2
公开(公告)日：2009-10-27
申请号：US11868306
申请日：2007-10-05
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
IPC分类号： H03B5/08
CPC分类号： H03L7/10 , H03L7/099
摘要： A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.
摘要翻译：锁相环（PLL）包括用于通过制造包括PLL的集成电路的过程变化校准用于电容变化的振荡电路的校准回路。存储用于在处理角设定PLL的频率的电容分布。在上电或空闲时间后，以两个频率进行校准。确定并存储在两个频率下操作锁相环的电容。在频率变化期间，操作PLL的电容由电容曲线和存储的电容确定。假设PLL的电容随频率线性变化，并且两个存储的电容用于通过在所选择的电容分布中的电容相加的两个存储的电容之间的线性内插来确定所选频率处的差电容，产生一个工作电容的频率。

7. 发明申请

US20090091396A1 METHOD AND SYSTEM FOR CALIBRATION OF A TANK CIRCUIT IN A PHASE LOCK LOOP 有权
标题翻译：用于在相位锁定环中校准电路的方法和系统
公开(公告)号：US20090091396A1
公开(公告)日：2009-04-09
申请号：US11868306
申请日：2007-10-05
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
IPC分类号： H03L7/099 , H03L7/08
CPC分类号： H03L7/10 , H03L7/099
摘要： A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances. The interpolated difference capacitance is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance. The capacitance of a tank circuit of the phase lock loop is set to the operating capacitance.
摘要翻译：锁相环包括用于通过制造包括锁相环的集成电路的过程变化来校准用于电容变化的储能电路的校准回路。用于设置过程角（例如典型过程角）的锁相环频率的电容分布存储在驱动软件或主机处理器中。在上电或空闲时间后，以两个频率进行校准。确定并存储在两个频率下操作锁相环的电容。在频率变化期间，根据电容曲线和存储的电容确定操作锁相环的电容。在一个方面，假设锁相环的电容随频率线性变化，并且两个存储的电容用于通过两个存储电容之间的线性内插来确定所选频率处的差电容。内插差分电容以所选频率加到电容分布中的电容上，以产生一个工作电容。锁相环的电路电容设定为工作电容。

8. 发明授权

US07394870B2 Low complexity synchronization for wireless transmission 有权
标题翻译：无线传输的低复杂度同步
公开(公告)号：US07394870B2
公开(公告)日：2008-07-01
申请号：US10407572
申请日：2003-04-04
申请人： Charles Chien , David Hsueh-Chia Chien
发明人： Charles Chien , David Hsueh-Chia Chien
IPC分类号： H04L27/00
CPC分类号： H04L7/042 , H04L7/0337
摘要： A receiver, system and method for providing symbol timing recovery that allows for inexpensive and low-complexity synchronization for communication systems. A receiver receives a signal including digital data in the form of packets that is transmitted from a transmitter. The receiver uses information contained in each of the packets to align a phase of the receiver clock with a phase of the transmitter clock. The receiver further controls a sampling device such that the in-phase (I) and quadrature (Q) components are sampled at an optimum sample rate and at an optimum instance of time without requiring a numerically controlled oscillator or voltage controlled oscillator.
摘要翻译：用于提供符号定时恢复的接收机，系统和方法，其允许用于通信系统的便宜且低复杂度的同步。接收机接收包含从发射机发送的分组形式的数字数据的信号。接收机使用包含在每个分组中的信息来将接收机时钟的相位与发射机时钟的相位对准。接收器进一步控制采样装置，使得同相（I）和正交（Q）分量以最佳采样率和最佳时间实例采样，而不需要数字振荡器或压控振荡器。

9. 发明授权

US07155654B2 Low complexity error concealment for wireless transmission 有权
标题翻译：无线传输的低复杂度错误隐藏
公开(公告)号：US07155654B2
公开(公告)日：2006-12-26
申请号：US10435176
申请日：2003-05-10
申请人： Charles Chien , David Hsueh-Chia Chien
发明人： Charles Chien , David Hsueh-Chia Chien
IPC分类号： H04L1/00 , G06F11/00
CPC分类号： H04L1/0071 , G11B20/10009 , H03M13/00 , H04L1/0019 , H04L1/0045 , H04L1/0072
摘要： An apparatus and method for concealing errors in digital data. An interpolator estimates a value of a sample of digital data from other samples of the digital data. The interpolator has an input for inputting the digital data and an output for outputting the estimated value of the sample of the digital data. A holding unit has an input for selectively receiving the sample of the digital data only when the sample is error free, and an output for outputting the error free sample. The input of the holding unit may be in parallel with the input of the interpolator. A selector selects between outputting the estimated value of the sample of the received digital data from an output of the interpolator and outputting the error free sample of the received digital data from an output of a holding unit based on at least one error indicator.
摘要翻译：一种用于隐藏数字数据中的错误的装置和方法。内插器估计来自数字数据的其他样本的数字数据样本的值。内插器具有用于输入数字数据的输入和用于输出数字数据的样本的估计值的输出。保持单元具有用于仅当样本无错误时有选择地接收数字数据的样本的输入和用于输出无错误样本的输出。保持单元的输入可以与内插器的输入并联。选择器选择从内插器的输出输出接收的数字数据的样本的估计值，并基于至少一个误差指示符从保持单元的输出输出接收到的数字数据的无错误采样。

10. 发明申请

US20060009171A1 LO leakage and sideband image calibration system and method 有权
标题翻译： LO泄漏和边带图像校准系统及方法
公开(公告)号：US20060009171A1
公开(公告)日：2006-01-12
申请号：US10888842
申请日：2004-07-09
申请人： Zhiwei Xu , Shan Jiang , Charles Chien
发明人： Zhiwei Xu , Shan Jiang , Charles Chien
IPC分类号： H04B1/02 , H04B1/04
CPC分类号： H04B1/0475
摘要： A system or method for calibrating an RF transmitter includes inputting a test tone to the RF transmitter. LO leakage calibration is performed on an output of the RF transmitter with the test tone inputted thereto, in order to determine a minimum LO leakage. Thereafter, sideband image calibration is performed on the output of the RF transmitter with the test tone inputted thereto, in order to determine a minimum sideband image. Operational values for the RF transmitter are stored in memory based on the detected minimum LO leakage and the detected minimum sideband image, to be used during a normal operation mode of the RF transmitter.
摘要翻译：用于校准RF发射机的系统或方法包括将测试音调输入到RF发射机。在输入了测试音的RF发射机的输出上执行LO泄漏校准，以便确定最小的LO泄漏。此后，对输入了测试音的RF发射机的输出执行边带图像校准，以便确定最小边带图像。基于检测到的最小LO泄漏和检测到的最小边带图像将RF发射机的操作值存储在存储器中，以在RF发射机的正常操作模式期间使用。

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