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1. 发明授权

US07292478B2 Non-volatile memory including charge-trapping layer, and operation and fabrication of the same 有权
标题翻译：非易失性存储器包括电荷捕获层，以及其操作和制造
公开(公告)号：US07292478B2
公开(公告)日：2007-11-06
申请号：US11222708
申请日：2005-09-08
申请人： Chao-Lun Yu , Chao-I Wu
发明人： Chao-Lun Yu , Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/42352
摘要： A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the trench. The gate includes a p-doped semiconductor material, so that the memory cell is particularly suitable to erase through hole injection from the gate.
摘要翻译：描述了非易失性存储单元，包括其中具有沟槽的半导体衬底，沟槽中的电荷俘获层，设置在沟槽中的栅极和至少由电荷俘获层与衬底分离的栅极，以及S / 在沟槽旁边的衬底中的D区域。栅极包括p掺杂的半导体材料，使得存储单元特别适合于通过从栅极注入空穴进行擦除。

2. 发明授权

US07759726B2 Non-volatile memory device, non-volatile memory cell thereof and method of fabricating the same 有权
标题翻译：非易失性存储器件，其非易失性存储单元及其制造方法
公开(公告)号：US07759726B2
公开(公告)日：2010-07-20
申请号：US11179294
申请日：2005-07-12
申请人： Chao-Lun Yu , Chao-I Wu
发明人： Chao-Lun Yu , Chao-I Wu
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4232 , H01L29/66833
摘要： The present invention disclosed a non-volatile memory device and fabricating method thereof. The structure of non-volatile memory device at least comprises a substrate, several dielectric strips, several bit lines, a dielectrically stacking multi-layer, and several word lines. The substrate has several recesses. The dielectric strips are formed on the substrate, and each of the recess is interposed between two adjacent dielectric strips. The bit lines are respectively formed on the dielectric strips. The dielectrically stacking multi-layer comprising a charge-trapping layer is disposed on the bit lines and the recesses. The word lines are formed on the dielectrically stacking multi-layer and intersecting to the bit lines. When a voltage is applied to the bit lines, a plurality of inversion regions are respectively generated on the substrate.
摘要翻译：本发明公开了一种非易失性存储器件及其制造方法。非易失性存储器件的结构至少包括衬底，多个介质条，几个位线，介电层叠多层和多个字线。基板有几个凹槽。介质条形成在基板上，并且每个凹槽介于两个相邻的介质条之间。位线分别形成在介质条上。包含电荷捕获层的介电层叠多层设置在位线和凹部上。字线形成在介电堆叠多层上并与位线相交。当对位线施加电压时，在基板上分别产生多个反转区域。

3. 发明申请

US20070063268A1 Non-volatile memory, and operation and fabrication of the same 有权
标题翻译：非易失性存储器，以及其操作和制造
公开(公告)号：US20070063268A1
公开(公告)日：2007-03-22
申请号：US11222708
申请日：2005-09-08
申请人： Chao-Lun Yu , Chao-I Wu
发明人： Chao-Lun Yu , Chao-I Wu
IPC分类号： H01L29/94
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/42352
摘要： A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the trench. The gate includes a p-doped semiconductor material, so that the memory cell is particularly suitable to erase through hole injection from the gate.
摘要翻译：描述了非易失性存储单元，包括其中具有沟槽的半导体衬底，沟槽中的电荷俘获层，设置在沟槽中的栅极和至少由电荷俘获层与衬底分离的栅极，以及S / 在沟槽旁边的衬底中的D区域。栅极包括p掺杂的半导体材料，使得存储单元特别适合于通过从栅极注入空穴进行擦除。

4. 发明申请

US20070012993A1 Non-volatile memory device, non-volatile memory cell thereof and method of fabricating the same 有权
标题翻译：非易失性存储器件，其非易失性存储单元及其制造方法
公开(公告)号：US20070012993A1
公开(公告)日：2007-01-18
申请号：US11179294
申请日：2005-07-12
申请人： Chao-Lun Yu , Chao-I Wu
发明人： Chao-Lun Yu , Chao-I Wu
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4232 , H01L29/66833
摘要： The present invention disclosed a non-volatile memory device and fabricating method thereof. The structure of non-volatile memory device at least comprises a substrate, several dielectric strips, several bit lines, a dielectrically stacking multi-layer, and several word lines. The substrate has several recesses. The dielectric strips are formed on the substrate, and each of the recess is interposed between two adjacent dielectric strips. The bit lines are respectively formed on the dielectric strips. The dielectrically stacking multi-layer comprising a charge-trapping layer is disposed on the bit lines and the recesses. The word lines are formed on the dielectrically stacking multi-layer and intersecting to the bit lines. When a voltage is applied to the bit lines, a plurality of inversion regions are respectively generated on the substrate.
摘要翻译：本发明公开了一种非易失性存储器件及其制造方法。非易失性存储器件的结构至少包括衬底，多个介质条，几个位线，介电层叠多层和多个字线。基板有几个凹槽。介质条形成在基板上，并且每个凹槽介于两个相邻的介质条之间。位线分别形成在介质条上。包含电荷捕获层的介电层叠多层设置在位线和凹部上。字线形成在介电堆叠多层上并与位线相交。当对位线施加电压时，在基板上分别产生多个反转区域。

5. 发明授权

US08467238B2 Dynamic pulse operation for phase change memory 有权
标题翻译：相变存储器的动态脉冲操作
公开(公告)号：US08467238B2
公开(公告)日：2013-06-18
申请号：US12946636
申请日：2010-11-15
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/0035
摘要： The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.
摘要翻译：控制电路进行改变阵列的相变存储单元的电阻状态的复位动作和设定动作。控制电路至少改变一个参数，至少一个复位操作和设置操作中的一个参数用于将来的操作。该更改响应于阵列的内存状态保留降级的指示符。

6. 发明授权

US08432745B2 High second bit operation window method for virtual ground array with two-bit memory cells 有权
标题翻译：具有两位存储单元的虚拟接地阵列的高二位操作窗口方法
公开(公告)号：US08432745B2
公开(公告)日：2013-04-30
申请号：US13184189
申请日：2011-07-15
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/00
CPC分类号： H01L21/28282 , G11C16/0475 , G11C16/0491 , H01L27/11568 , H01L29/7923
摘要： A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.
摘要翻译：公开了一种采用存储器半导体单元的非易失性VG存储器阵列，该存储器半导体单元能够存储与至少一个电绝缘层（例如氧化物）相结合的分层的非导电电荷俘获电介质（例如氮化硅）的两比特信息。。存储器阵列的位线能够传输正电压以到达阵列的存储器单元的源极/漏极区域。公开了一种方法，其包括将阵列的存储单元的空穴注入擦除将存储单元的电压阈值降低到低于单元的初始电压阈值的值。空穴注入诱导的较低电压阈值降低了第二位效应，使得位的编程和未编程电压阈值之间的操作窗口变宽。编程和读取步骤减少阵列中存储单元的泄漏电流。

7. 发明授权

US08378382B2 High aspect-ratio PN-junction and method for manufacturing the same 有权
标题翻译：高纵横比PN结及其制造方法
公开(公告)号：US08378382B2
公开(公告)日：2013-02-19
申请号：US11027807
申请日：2004-12-30
申请人： Chao-I Wu , Ming Hsiu Lee
发明人： Chao-I Wu , Ming Hsiu Lee
IPC分类号： H01L29/66 , H01L29/861
CPC分类号： H01L27/0814 , H01L27/1021 , H01L29/8613
摘要： A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.
摘要翻译：提供了具有高纵横比PN结的半导体器件。半导体器件包括导电层。半导体器件还包括形成在导电层上的多个第一掺杂区域。掺杂区域的侧壁被掺杂以形成PN结。半导体器件还包括在第一掺杂区域上的多个第二掺杂区域。

8. 发明授权

US08363463B2 Phase change memory having one or more non-constant doping profiles 有权
标题翻译：具有一个或多个非恒定掺杂分布的相变存储器
公开(公告)号：US08363463B2
公开(公告)日：2013-01-29
申请号：US12729837
申请日：2010-03-23
申请人： Yen-Hao Shih , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung H Lam
发明人： Yen-Hao Shih , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung H Lam
IPC分类号： G11C11/00
CPC分类号： H01L45/1625 , G11C13/0004 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1641
摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
摘要翻译：一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布。根据不同的晶体学，热学和电学条件以及不同的相变条件，使用非恒定浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

9. 发明授权

US08295094B2 Method of operating non-volatile memory cell 有权
标题翻译：操作非易失性存储单元的方法
公开(公告)号：US08295094B2
公开(公告)日：2012-10-23
申请号：US13168536
申请日：2011-06-24
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34
CPC分类号： H01L21/28282 , G11C16/0408 , G11C16/0466 , G11C16/107 , H01L29/78654 , H01L29/792
摘要： A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type are injected into the charge storage layer by applying FN voltages.
摘要翻译：本发明的3D阵列的存储单元的操作方法如下。通过在存储单元的双面施加双面偏置（DSB）电压将第一类型的载体注入存储单元的电荷存储层。通过施加FN电压将第二类型的载体注入电荷存储层。

10. 发明申请

US20120120723A1 Dynamic Pulse Operation for Phase Change Memory 有权
标题翻译：相变存储器的动态脉冲操作
公开(公告)号：US20120120723A1
公开(公告)日：2012-05-17
申请号：US12946636
申请日：2010-11-15
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/21
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/0035
摘要： The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.
摘要翻译：控制电路进行改变阵列的相变存储单元的电阻状态的复位动作和设定动作。控制电路至少改变一个参数，至少一个复位操作和设置操作中的一个参数用于将来的操作。该变化响应于阵列的内存状态保持降低的指示符。

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