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1. 发明申请

US20170084696A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20170084696A1
公开(公告)日：2017-03-23
申请号：US15259941
申请日：2016-09-08
申请人： Changhyun Lee , Heonkyu Lee , Shinhwan Kang , Youngwoo Park
发明人： Changhyun Lee , Heonkyu Lee , Shinhwan Kang , Youngwoo Park
IPC分类号： H01L29/10 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565
摘要： A three-dimensional semiconductor memory device includes a stack on a substrate including electrodes vertically stacked on a substrate, lower insulating patterns disposed between the stack and the substrate, the lower insulating patterns being adjacent to both sidewalls of the stack and being spaced apart from each other, a plurality of vertical structures penetrating the stack and being connected to the substrate, and a data storing pattern between the stack and the vertical structures, the data storing pattern including a portion disposed between the lowermost one of the electrodes and the substrate.

2. 发明授权

US08829589B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US08829589B2
公开(公告)日：2014-09-09
申请号：US13757273
申请日：2013-02-01
申请人： Changhyun Lee , Byoungkeun Son , Youngwoo Park
发明人： Changhyun Lee , Byoungkeun Son , Youngwoo Park
IPC分类号： H01L29/788 , H01L29/04 , H01L29/792
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/04 , H01L29/7889 , H01L29/792 , H01L29/7926
摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.
摘要翻译：三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。分离图案可以包括至少一个分离半导体层。

3. 发明授权

US08643080B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US08643080B2
公开(公告)日：2014-02-04
申请号：US13217416
申请日：2011-08-25
申请人： Changhyun Lee , Byoungkeun Son , Youngwoo Park
发明人： Changhyun Lee , Byoungkeun Son , Youngwoo Park
IPC分类号： H01L29/788 , H01L29/792 , H01L21/06 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11556 , H01L29/7889 , H01L29/7926
摘要： Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.
摘要翻译：提供三维半导体器件。这些装置可以包括配置成从基板向上延伸的间隙填充绝缘图案和由间隙填充绝缘图案的侧壁限定的电极结构。可以在相邻的间隙填充绝缘图案之间提供垂直结构以穿透电极结构，并且垂直结构可以包括垂直结构的第一行和第二行。可以在第一和第二排垂直结构之间提供分离图案，并且包括分离半导体层。分离图案沿着平行于第一和第二排垂直结构的方向延伸。

4. 发明授权

US09947686B2 Semiconductor device including a stack having a sidewall with recessed and protruding portions 有权
公开(公告)号：US09947686B2
公开(公告)日：2018-04-17
申请号：US15456841
申请日：2017-03-13
申请人： Byoungkeun Son , Yoocheol Shin , Changhyun Lee , Hyunjung Kim , Chung-Il Hyun
发明人： Byoungkeun Son , Yoocheol Shin , Changhyun Lee , Hyunjung Kim , Chung-Il Hyun
IPC分类号： H01L29/788 , H01L27/11582 , H01L27/11565 , H01L21/28 , H01L27/1157
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
摘要： A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

5. 发明授权

US09147471B2 Nonvolatile memory device and driving method thereof 有权
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：US09147471B2
公开(公告)日：2015-09-29
申请号：US13654973
申请日：2012-10-18
申请人： Changhyun Lee
发明人： Changhyun Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459
摘要： According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.
摘要翻译：根据示例性实施例，非易失性存储器件包括具有多个串联连接的选择晶体管和与串联连接的选择晶体管的一端串联连接的多个存储单元的多个串。控制逻辑被配置为执行用于设置串联连接的选择晶体管中的至少一个的阈值电压的编程操作。

6. 发明授权

US08872183B2 Three-dimensional semiconductor devices 有权
标题翻译：三维半导体器件
公开(公告)号：US08872183B2
公开(公告)日：2014-10-28
申请号：US13366057
申请日：2012-02-03
申请人： Sung-Il Chang , Changhyun Lee , Byoungkeun Son , Jin-Soo Lim
发明人： Sung-Il Chang , Changhyun Lee , Byoungkeun Son , Jin-Soo Lim
IPC分类号： H01L29/04 , H01L21/822 , H01L27/115 , H01L27/06
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/8221 , H01L27/0688 , H01L27/11556 , H01L29/4232 , H01L29/42372
摘要： Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.
摘要翻译：提供三维半导体器件。三维半导体器件包括衬底，衬底上的缓冲层。缓冲层包括具有相对于衬底的蚀刻选择性的材料。在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。还讨论了相关的制造方法。

7. 发明授权

US08737129B2 Nonvolatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US08737129B2
公开(公告)日：2014-05-27
申请号：US13355834
申请日：2012-01-23
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/10 , G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C29/00
摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.
摘要翻译：非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线以及当执行编程操作时，对未选字线的取消选择读取电压。电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上当执行读操作时，字线和与选择字线相邻的下字线。

8. 发明申请

US20140042520A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20140042520A1
公开(公告)日：2014-02-13
申请号：US14057380
申请日：2013-10-18
申请人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
摘要翻译：三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如，N型）的公共源极区的衬底。凹部部分（或完全）延伸穿过公共源区域。衬底上的垂直堆叠的非易失性存储器单元包括间隔开的栅电极的垂直堆叠和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直堆叠的侧壁上并在凹槽的侧壁上延伸。栅极电介质层在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。

9. 发明授权

US08278170B2 Methods of forming nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein 有权
标题翻译：形成其中具有垂直集成的非易失性存储单元子串的非易失性存储器件的方法
公开(公告)号：US08278170B2
公开(公告)日：2012-10-02
申请号：US13165576
申请日：2011-06-21
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L21/336
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

10. 发明授权

US09343154B2 Nonvolatile memory device and driving method thereof 有权
公开(公告)号：US09343154B2
公开(公告)日：2016-05-17
申请号：US14819428
申请日：2015-08-06
申请人： Changhyun Lee
发明人： Changhyun Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459
摘要： According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.

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