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1. 发明授权

US08786353B2 Multi-channel semiconductor device and display device comprising same 有权
标题翻译：多通道半导体器件和包括其的显示器件
公开(公告)号：US08786353B2
公开(公告)日：2014-07-22
申请号：US13304473
申请日：2011-11-25
申请人： Jae-wook Kwon , Chang-ho An , Ki-won Seo , Sung-ho Lee
发明人： Jae-wook Kwon , Chang-ho An , Ki-won Seo , Sung-ho Lee
IPC分类号： H03K17/28 , H03K17/00 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/006 , G09G2310/0297
摘要： A multi-channel semiconductor device comprises a plurality of buffer groups each comprising at least one output buffer, a plurality of pad groups each comprising at least one output pad, and a channel switching portion that controls connection between the plurality of buffer groups and the plurality of pad groups. One of the pad groups outputs an output signal of one of the buffer groups in a first operation mode and sequentially outputs output signals of all of the buffer groups in a second operation mode.
摘要翻译：多通道半导体器件包括多个缓冲器组，每个缓冲器组包括至少一个输出缓冲器，每个包括至少一个输出焊盘的多个焊盘组以及控制多个缓冲器组与多个缓冲器组之间的连接的通道切换部分的垫组。其中一个焊盘组以第一操作模式输出一个缓冲组的输出信号，并在第二操作模式中顺序地输出所有缓冲组的输出信号。

2. 发明授权

US08466909B2 Output buffer having high slew rate, method of controlling output buffer, and display driving device including output buffer 有权
标题翻译：具有高压摆率的输出缓冲器，控制输出缓冲器的方法以及包括输出缓冲器的显示驱动装置
公开(公告)号：US08466909B2
公开(公告)日：2013-06-18
申请号：US12941459
申请日：2010-11-08
申请人： Chang-ho An , Jae-wook Kwon , Ki-won Seo , Sung-ho Lee
发明人： Chang-ho An , Jae-wook Kwon , Ki-won Seo , Sung-ho Lee
IPC分类号： G06F3/038 , G09G5/00 , G09G3/36
CPC分类号： G09G3/3614 , G09G3/3688 , G09G2320/0252
摘要： An output buffer having a high slew rate, a method of controlling the output buffer, and a display driving device including the output buffer. The output buffer includes: a first output buffer adapted to output a source line driving signal to a first output terminal in response to a first control signal and output a source driving signal to a second output terminal in response to a second control signal; a second output buffer adapted to output a source line driving signal to a third output terminal in response to the first control signal and output a source line driving signal to a fourth output terminal in response to the second control signal; and a feedback circuit for connecting the first through fourth output terminals to negative input terminals of the first and second output buffers in response to the first control signal and the second control signal.
摘要翻译：具有高压摆率的输出缓冲器，控制输出缓冲器的方法以及包括输出缓冲器的显示驱动装置。输出缓冲器包括：第一输出缓冲器，用于响应于第一控制信号将源极线驱动信号输出到第一输出端，并响应于第二控制信号将源驱动信号输出到第二输出端; 第二输出缓冲器，用于响应于所述第一控制信号将源极线驱动信号输出到第三输出端，并响应于所述第二控制信号将源极线驱动信号输出到第四输出端; 以及反馈电路，用于响应于第一控制信号和第二控制信号将第一至第四输出端连接到第一和第二输出缓冲器的负输入端。

3. 发明申请

US20120127386A1 MULTI-CHANNEL SEMICONDUCTOR DEVICE AND DISPLAY DEVICE COMPRISING SAME 有权
标题翻译：多通道半导体器件和包含其的显示器件
公开(公告)号：US20120127386A1
公开(公告)日：2012-05-24
申请号：US13304473
申请日：2011-11-25
申请人： Jae-wook Kwon , Chang-ho An , Ki-won Seo , Sung-ho Lee
发明人： Jae-wook Kwon , Chang-ho An , Ki-won Seo , Sung-ho Lee
IPC分类号： G02F1/136 , H03K17/00
CPC分类号： G09G3/3688 , G09G3/006 , G09G2310/0297
摘要： A multi-channel semiconductor device comprises a plurality of buffer groups each comprising at least one output buffer, a plurality of pad groups each comprising at least one output pad, and a channel switching portion that controls connection between the plurality of buffer groups and the plurality of pad groups. One of the pad groups outputs an output signal of one of the buffer groups in a first operation mode and sequentially outputs output signals of all of the buffer groups in a second operation mode.
摘要翻译：多通道半导体器件包括多个缓冲器组，每个缓冲器组包括至少一个输出缓冲器，每个包括至少一个输出焊盘的多个焊盘组以及控制多个缓冲器组与多个缓冲器组之间的连接的通道切换部分的垫组。其中一个焊盘组以第一操作模式输出一个缓冲组的输出信号，并在第二操作模式中顺序地输出所有缓冲组的输出信号。

4. 发明授权

US08264262B2 Delay-locked loop circuit and semiconductor device including the same 有权
标题翻译：延迟锁定环路电路和包括其的半导体器件
公开(公告)号：US08264262B2
公开(公告)日：2012-09-11
申请号：US12950380
申请日：2010-11-19
申请人： Chang-ho An
发明人： Chang-ho An
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A delay-locked loop (DDL) circuit and a semiconductor device including the same are provided. The DDL circuit includes: a control voltage generator for generating a control voltage corresponding to a delay difference between an input clock and a plurality of comparison clocks by comparing the input clock with the plurality of comparison clocks that are sequentially generated and have different delays; a pulse width adjuster for adjusting a pulse width of the input clock according to a delay difference between the input clock and an arbitrary comparison clock of the comparison clocks and for generating a pulse-width-adjusted input clock as an adjusted input clock; and a delay unit for delaying the adjusted input clock in response to the control voltage and for outputting the delayed adjusted input clock as the comparison clocks and output clocks.
摘要翻译：提供了延迟锁定环路（DDL）电路和包括该延迟锁定环路的半导体器件。 DDL电路包括：控制电压发生器，用于通过将输入时钟与顺序生成并具有不同延迟的多个比较时钟进行比较来产生对应于输入时钟和多个比较时钟之间的延迟差的控制电压; 脉冲宽度调节器，用于根据输入时钟和比较时钟的任意比较时钟之间的延迟差来调节输入时钟的脉冲宽度，并产生脉冲宽度调整的输入时钟作为经调整的输入时钟; 以及延迟单元，用于响应于控制电压延迟调整的输入时钟，并用于输出延迟调整的输入时钟作为比较时钟和输出时钟。

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