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    • 2. 发明授权
    • Method for finding minimal signed digit with variable multi-bit coding based on booth's algorithm
    • 基于展位算法的可变多位编码寻找最小签名数字的方法
    • US08150899B2
    • 2012-04-03
    • US11952477
    • 2007-12-07
    • Dae-Won KimSeong-Woon KimMyung-Joon Kim
    • Dae-Won KimSeong-Woon KimMyung-Joon Kim
    • G06F5/00
    • G06F7/5332
    • Provided is a method for finding a minimal signed digit with variable multi-bit coding. The method includes the steps of: scanning and grouping given multi-bit and checking the type of each group; deciding whether each group is to be performed by any one of a coding for positive number and a coding of negative number depending on the type of each group; converting the value of each group into a corresponding value of different number system and finding a signed digit based on the converted value; if the type of each group indicates the coding for negative number, performing bitwise inverting on the value of each group; and converting multi-bit subjected to the bitwise inverting into a corresponding value of different number system, and finding a signed digit based on the converted value.
    • 提供了一种用于使用可变多位编码来找到最小有符号数字的方法。 该方法包括以下步骤:扫描和分组给定的多位并检查每个组的类型; 根据每个组的类型来决定是否要对编号正数和负数编码中的任何一个执行每个组; 将每组的值转换为不同数字系统的对应值,并根据转换后的值找到有符号数字; 如果每个组的类型指示编号为负数,则对每组的值执行逐位倒置; 并将经过逐位反转的多位转换成不同数量系统的对应值,并且基于转换的值找到有符号数字。
    • 4. 发明授权
    • PCI express packet filter including descrambler
    • PCI express包过滤器包括解扰器
    • US07957294B2
    • 2011-06-07
    • US11633046
    • 2006-12-01
    • Yong-Seok ChoiSeong-Woon KimMyung-Joon Kim
    • Yong-Seok ChoiSeong-Woon KimMyung-Joon Kim
    • H04L12/26H04J3/16G06F13/12G06F13/20H04L29/06
    • H04L69/12H04L69/323H04L69/324
    • A packet detecting device used in a receiver employing PCI Express protocol is disclosed. The packet detecting device includes: a physical layer packet detecting unit for detecting a physical layer packet from a PCI express packet received and parallelized to 16 bit data through a physical deserializer; a descrambling unit for descrambling a physical layer packet from a PCI express packet received and parallelized to 16 bit data through a physical deserializer; a data link layer packet detecting unit for detecting a data link layer packet from a descrambled packet outputted from the descrambling unit; and a transaction layer packet detecting unit for detecting a transaction layer packet from a descrambled packet outputted from the descrambling unit.
    • 公开了一种在采用PCI Express协议的接收机中使用的分组检测装置。 分组检测装置包括:物理层分组检测单元,用于通过物理解串器从接收并并行化到16位数据的PCI express分组中检测物理层分组; 解扰单元,用于通过物理解串器将来自PCI express分组的物理层分组解扰并接收并并行化为16位数据; 数据链路层分组检测单元,用于从解扰单元输出的解扰分组中检测数据链路层分组; 以及事务层分组检测单元,用于从解扰单元输出的解扰分组中检测事务层分组。
    • 5. 发明授权
    • Apparatus for searching TCP and UDP sockets
    • 用于搜索TCP和UDP套接字的设备
    • US07751346B2
    • 2010-07-06
    • US11605801
    • 2006-11-29
    • Chan-Ho ParkSeong-Woon KimMyung-Joon Kim
    • Chan-Ho ParkSeong-Woon KimMyung-Joon Kim
    • H04L12/28
    • H04L69/16H04L69/12H04L69/161H04L69/162
    • An apparatus for searching a socket ID of a received packet in a transmission control protocol (TCP) and a user datagram protocol (UDP) is provided. The apparatus includes: a master module, a branch table module and a tree table module. The master module analyzes command information from a processor, transfers commands to the branch table module and to the tree table module, receives results from the branch table module and from the tree table module, and reports the received results to the processor. The branch table module receives commands from the master module and manages a branch table by using only the lower 10 bits of a simple internet protocol (IP) address of the commands. The tree table module is coupled to the master module and to the branch table module, in which the tree table module manages a binary tree.
    • 提供了一种用于在传输控制协议(TCP)和用户数据报协议(UDP)中搜索接收到的分组的套接字ID的装置。 该装置包括:主模块,分支表模块和树形表模块。 主模块从处理器分析命令信息,将命令传送到分支表模块和树形表模块,从分支表模块和树形表模块接收结果,并将接收到的结果报告给处理器。 分支表模块从主模块接收命令,并通过仅使用命令的简单互联网协议(IP)地址的低10位来管理分支表。 树表模块耦合到主模块和分支表模块,树模块管理二叉树。
    • 6. 发明申请
    • WRAPPER CIRCUIT FOR GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS SYSTEM AND METHOD FOR OPERATING THE SAME
    • 用于全球异地同步同步系统的封装电路及其操作方法
    • US20090150706A1
    • 2009-06-11
    • US12186114
    • 2008-08-05
    • Myeong-Hoon OHSeong-Woon KimMyung-Joon KimSung-Nam Kim
    • Myeong-Hoon OHSeong-Woon KimMyung-Joon KimSung-Nam Kim
    • G06F1/12H04L7/00
    • G06F1/08G06F1/3203
    • Provided are a high-performance wrapper circuit for a globally asynchronous locally synchronous (GALS) system and a synchronization method using the same, which are capable of solving a synchronization problem caused when data are transmitted between locally synchronous modules employing different clocks, and a method for operating the wrapper circuit. The GALS system includes a clock generator for supplying an operation clock to a locally synchronous module, a sender port for transmitting data to the outside according to a data transmission request signal output from the locally synchronous module, and generating a first clock stop signal for stopping an operation of the clock generator, and a receiver port for receiving data from the outside, and generating a second clock stop signal for stopping the operation of the clock generator. The sender port generates the first clock stop signal to the clock generator when a next data transmission request signal is received before completing a data transmission performed by a previous data transmission request signal output from the locally synchronous module.
    • 提供了一种用于全球异步本地同步(GALS)系统的高性能封装电路和使用该高性能封装电路的同步方法,其能够解决当采用不同时钟的本地同步模块之间传输数据时引起的同步问题,以及方法 用于操作包装电路。 GALS系统包括用于向本地同步模块提供操作时钟的时钟发生器,用于根据从本地同步模块输出的数据发送请求信号向外部发送数据的发送器端口,以及生成用于停止的第一时钟停止信号 时钟发生器的操作和用于从外部接收数据的接收器端口,以及产生用于停止时钟发生器的操作的第二时钟停止信号。 当在完成由本地同步模块输出的先前数据传输请求信号执行的数据传输之前接收到下一个数据传输请求信号时,发送器端口产生到时钟发生器的第一个时钟停止信号。
    • 9. 发明授权
    • Delay insensitive data transfer apparatus with low power consumption
    • 延迟不敏感的数据传输设备,功耗低
    • US07885254B2
    • 2011-02-08
    • US11927972
    • 2007-10-30
    • Myeong-Hoon OhSeong-Woon KimMyung-Joon Kim
    • Myeong-Hoon OhSeong-Woon KimMyung-Joon Kim
    • H04L12/50H04L12/28
    • H04L25/49H04L25/0264H04L25/4906
    • Provided is a delay insensitive (DI) data transfer apparatus with low power consumption. The apparatus, includes: N number of encoders configured to receive and encode input request and data signals, where each of the N number of encoders includes: a reference current source circuit configured to generate a current; and a voltage-to-current converter circuit configured to output a current having a level of 0, output the current having the level of I, and output the current having the level of 2I; and N number of decoders configured to recover the current-level signals, where each of the decoders includes: a threshold current source circuit configured to generate first and second threshold currents; an input current mirror circuit configured to differentiate the first and second threshold currents; and a current-to-voltage converter circuit configured to detect the threshold current, recover a voltage input value, and extract data and request signals.
    • 提供具有低功耗的延迟不敏感(DI)数据传送装置。 该装置包括:N个编码器,被配置为接收和编码输入请求和数据信号,其中N个编码器中的每一个包括:参考电流源电路,被配置为产生电流; 以及电压 - 电流转换器电路,被配置为输出电平为0的电流,输出具有电平I的电流,并输出电平为2I的电流; N个解码器被配置为恢复当前电平信号,其中每个解码器包括:阈值电流源电路,被配置为产生第一和第二阈值电流; 配置成区分第一和第二阈值电流的输入电流镜电路; 以及电流 - 电压转换器电路,被配置为检测阈值电流,恢复电压输入值,并提取数据和请求信号。