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1. 发明授权

US5124780A Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planarization 失效
标题翻译：导电接触插塞和使用激光平面化在集成电路中形成导电接触插塞的方法
公开(公告)号：US5124780A
公开(公告)日：1992-06-23
申请号：US713187
申请日：1991-06-10
申请人： Gurtej S. Sandhu , Chang Yu , Trung T. Doan , Mark E. Tuttle
发明人： Gurtej S. Sandhu , Chang Yu , Trung T. Doan , Mark E. Tuttle
IPC分类号： H01L21/28 , H01L21/321 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53223 , H01L21/32115 , H01L21/7684 , H01L21/76879 , H01L2924/0002
摘要： The invention is a method of forming a conductive contact plug and an interconnect line independent of each other. The contact plug is formed using laser planarization and a blanket etch back. The invention is also the contact plug thus formed. The contact plug and interconnect line may be fabricated with conductive materials having substantially similar methods of deposition. The integrity of the contact plug is enhanced using laser planarization.The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. A masking step defines a contact hole. An etch creates the contact hole which passes through the dielectric layer to a conductive region where contact is to be made. A first layer of conductive material is then deposited overlying the dielectric layer. A layer of material having an anti-reflective coating (ARC) (or a layer of material having a higher boiling point than the first layer) is deposited overlying the first layer. The ARC enhances the fluidity of the first layer during a subsequent laser planarization. The first layer and ARC overlying the dielectric are then laser planarized. The laser planarization is followed by a blanket etch of the first layer and ARC. The etch forms a contact plug substantially coplanar with the surface of the dielectric layer. At this juncture a second layer of conductive material may be deposited and masked to form interconnect lines for joining contact plugs.
摘要翻译：本发明是形成彼此独立的导电接触插塞和互连线的方法。接触塞是使用激光平面化和毯式回蚀而形成的。本发明也是如此形成的接触塞。接触插塞和互连线可以用具有基本相似的沉积方法的导电材料制成。使用激光平面化增强了接触插塞的完整性。该方法开始于具有介电层的晶片，其上表面已被平坦化。掩模步骤限定接触孔。蚀刻产生穿过介电层的接触孔到要进行接触的导电区域。然后将第一层导电材料沉积在电介质层上。具有抗反射涂层（ARC）（或具有比第一层沸点高的材料层）的材料层沉积在第一层上。 ARC在随后的激光平面化期间增强了第一层的流动性。然后将覆盖电介质的第一层和ARC激光平面化。激光平面化之后是第一层和ARC的毯式蚀刻。蚀刻形成与电介质层的表面基本上共面的接触插塞。在这个时刻，第二层导电材料可以被沉积和掩蔽以形成用于连接接触插塞的互连线。

2. 发明授权

US5094977A Stress reduction in metal films by laser annealing 失效
标题翻译：通过激光退火对金属膜进行应力减小
公开(公告)号：US5094977A
公开(公告)日：1992-03-10
申请号：US645865
申请日：1991-01-25
申请人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
发明人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
IPC分类号： H01L21/285 , H01L21/321
CPC分类号： H01L21/321 , H01L21/28518 , Y10S148/09 , Y10S148/093
摘要： A method of processing a semiconductor wafer comprises, a) chemical vapor depositing (CVD) a metal layer atop a semiconductor substrate; and b) impinging laser energy upon the CVD metal layer at an optical fluence of from 0.05 Joules/cm.sup.2 to 0.30 Joules/cm.sup.2 for a period of time sufficient to relieve mechanical stress associated with the CVD metal layer yet insufficient to melt the CVD metal layer. In accordance with another aspect of the invention, such treatment method could also be used to form a desired silicide layer in the same step.
摘要翻译：一种处理半导体晶片的方法包括：a）化学气相沉积（CVD）在半导体衬底顶上的金属层; 和b）以0.05焦耳/厘米2至0.30焦耳/平方厘米的光能密度将激光能量照射在CVD金属层上足以缓解与CVD金属层相关的机械应力但不足以熔化CVD金属层的时间。根据本发明的另一方面，这种处理方法也可用于在同一步骤中形成所需的硅化物层。

3. 发明授权

US5236865A Method for simultaneously forming silicide and effecting dopant activation on a semiconductor wafer 失效
标题翻译：同时形成硅化物并在半导体晶片上实现掺杂剂活化的方法
公开(公告)号：US5236865A
公开(公告)日：1993-08-17
申请号：US900557
申请日：1992-06-18
申请人： Gurtej S. Sandhu , Trung T. Doan , Chang Yu
发明人： Gurtej S. Sandhu , Trung T. Doan , Chang Yu
IPC分类号： H01L21/265 , H01L21/285 , H01L21/324
CPC分类号： H01L21/26513 , H01L21/28518 , H01L21/324
摘要： A method for forming silicides while simultaneously activating underlying silicon substrate active regions eliminates the need for separate annealing of the active region following ion-implantation procedures. The required energy for such simultaneous processing is provided by laser irradiation directed to the surface of a wafer after blanketing it with a layer of the metal desired in the silicide.
摘要翻译：在同时激活下游硅衬底有源区的同时形成硅化物的方法消除了在离子注入过程之后对活性区的单独退火的需要。用于这种同时处理的所需能量通过在用硅化物中所需的金属层覆盖之后被引导到晶片表面的激光照射来提供。

4. 发明授权

US5202278A Method of forming a capacitor in semiconductor wafer processing 失效
标题翻译：在半导体晶片加工中形成电容器的方法
公开(公告)号：US5202278A
公开(公告)日：1993-04-13
申请号：US757197
申请日：1991-09-10
申请人： Viju K. Mathews , Chang Yu , Mark E. Tuttle , Trung T. Doan
发明人： Viju K. Mathews , Chang Yu , Mark E. Tuttle , Trung T. Doan
IPC分类号： H01L21/02
CPC分类号： H01L28/82 , Y10S438/964
摘要： A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590.degree. and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm.sup.2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.
摘要翻译：一种在半导体水处理中形成电容器的方法，包括以下步骤：a）在硅晶片顶上提供导电掺杂的多晶硅第一层至第一厚度; b）在导电掺杂的第一多晶硅层上沉积未掺杂的第二多晶硅层至第二厚度，所述未掺杂多晶硅层在至少590°的沉积温度下沉积并具有上表面; c）以0.3J / cm 2或更大的激光能量密度将激光能量照射到第二多晶硅层的上表面上以使上表面粗糙化，从而增加第二多晶硅层的电容; d）图案化和蚀刻第一和第二多晶硅层以限定下电容器板; e）在粗糙化的第二多晶硅层上表面的上方提供电容器电介质层; 以及f）在电容器电介质顶部提供导电材料层以限定上电容器板。

5. 发明授权

US5173441A Laser ablation deposition process for semiconductor manufacture 失效
标题翻译：用于半导体制造的激光烧蚀沉积工艺
公开(公告)号：US5173441A
公开(公告)日：1992-12-22
申请号：US653658
申请日：1991-02-08
申请人： Chang Yu , Trung T. Doan
发明人： Chang Yu , Trung T. Doan
IPC分类号： C23C14/04 , C23C14/28 , H01L21/3205 , H05K3/20
CPC分类号： H01L21/32051 , C23C14/048 , C23C14/28 , H05K3/20 , Y10S438/94
摘要： A semiconductor manufacturing process for laser ablation deposition (LAD) in which metal features are written from a source substrate onto a target substrate. The source substrate and target substrate are mounted in close proximity to one another within a vacuum chamber. A laser beam is scanned in a programmed sequence or selected pattern through a transparent target substrate and onto a metallic film formed on the source substrate. Ablation of the metal film and deposition onto the target substrate may be closely controlled by the laser being focused directly at the metal film on the source substrate and by the selection of a source substrate having a suitable thermal conductivity. The process may be further controlled by selective heating of the source substrate. The process can be used to ablate and deposit a single or multiple metal layers on the target substrate. Additionally, the target substrate may be an optically transparent substrate so that the process may be used to fabricate photomask, electro-optic, and acousto-optic devices, transducers, and integrated circuits on insulator substrate.
摘要翻译：一种用于激光烧蚀沉积（LAD）的半导体制造工艺，其中将金属特征从源极衬底写入目标衬底。源极衬底和靶衬底在真空室内彼此靠近地安装。激光束以编程的顺序或选定的图案通过透明的目标衬底扫描到形成在源极衬底上的金属膜上。可以通过激光直接聚焦在源极基板上的金属膜上并通过选择具有合适导热性的源极衬底来严格控制金属膜的消融和沉积到目标衬底上。可以通过选择性加热源底物来进一步控制该过程。该方法可用于在目标基底上烧蚀和沉积单个或多个金属层。此外，目标衬底可以是光学透明衬底，使得该工艺可用于制造绝缘体衬底上的光掩模，电光和声光器件，换能器和集成电路。

6. 发明授权

US5139967A Process for planarizing insulating dielectric material 失效
标题翻译：平面化绝缘电介质材料的工艺
公开(公告)号：US5139967A
公开(公告)日：1992-08-18
申请号：US658987
申请日：1991-02-20
申请人： Gurtej S. Sandhu , Trung T. Doan , Chang Yu
发明人： Gurtej S. Sandhu , Trung T. Doan , Chang Yu
IPC分类号： H01L21/3105
CPC分类号： H01L21/3105
摘要： A method of processing a semiconductor wafer comprises the following sequential steps:selectively fabricating a semiconductor wafer in multilevels to produce desired electronic devices and integrated circuits on the wafer, the selective fabrication resulting in an irregular upper surface topography;applying a coating of insulating dielectric material having a melting point of less than or equal to about 850.degree. C. atop the fabricated wafer; andselectively impinging laser energy upon the dielectric coating for a selected period of time to at least partially melt the dielectric coating and cause its upper surface to become planarized.
摘要翻译：一种处理半导体晶片的方法包括以下顺序步骤：选择性地制造多层次的半导体晶片以在晶片上产生所需的电子器件和集成电路，所述选择性制造导致不规则的上表面形貌; 在制造的晶片顶上施加熔点小于或等于约850℃的绝缘介电材料涂层; 并且选择性地将激光能量照射在电介质涂层上一段选定的时间段以至少部分地熔化介质涂层并使其上表面变平坦化。

7. 发明授权

US5032233A Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point metal as an anti-reflective coating during laser planarization 失效
标题翻译：在激光平面化期间通过使用高熔点金属作为抗反射涂层来改善集成电路上的金属化层的台阶覆盖的方法
公开(公告)号：US5032233A
公开(公告)日：1991-07-16
申请号：US578545
申请日：1990-09-05
申请人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
发明人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
IPC分类号： H01L21/28 , H01L21/321 , H01L21/768
CPC分类号： H01L21/32115 , H01L21/7684
摘要： A method for improving step coverage of metallization layers of an aluminum alloy on an integrated circuit involves use of a deposited layer of a high melting point metal, such as tungsten or an alloy of tungsten and titanium, as an anti-reflective coating (ARC) to increase the efficient use of laser energy for planarization purposes where the underlying aluminum alloy covers a step, such as at an open via.
摘要翻译：一种用于提高集成电路中的铝合金的金属化层的台阶覆盖率的方法包括使用诸如钨或钨和钛的合金的高熔点金属的沉积层作为抗反射涂层（ARC）以增加用于平面化目的的激光能量的有效使用，其中下面的铝合金覆盖了台阶，例如在开口处。

8. 发明授权

US5380678A Bilayer barrier metal method for obtaining 100% step-coverage in contact vias without junction degradation 失效
标题翻译：双层阻挡金属法，用于在没有结层退化的接触通孔中获得100％的阶梯覆盖
公开(公告)号：US5380678A
公开(公告)日：1995-01-10
申请号：US667955
申请日：1991-03-12
申请人： Chang Yu , Trung T. Doan
发明人： Chang Yu , Trung T. Doan
IPC分类号： H01L21/768 , H01L21/441 , H01L21/324
CPC分类号： H01L21/76843 , H01L21/76877
摘要： A process for forming an electrical connection in a semiconductor device between an aluminum interconnect and the substrate avoids junction spiking at temperatures (1000.degree. C.-1500.degree. C.) significantly above the standard semiconductor device fabrication temperatures (
摘要翻译：用于在铝互连和衬底之间的半导体器件中形成电连接的工艺避免了在标准半导体器件制造温度（<500℃）以下的温度（1000℃〜1500℃）的结尖峰。在衬底的上表面上形成绝缘层，其中通孔通过绝缘层形成，以露出将要进行电连接的衬底的一部分。在绝缘层和基板的暴露部分之上形成第一难熔金属阻挡层。优选地，第一阻挡层是TiN。在第一阻挡层上方形成第二难熔金属阻挡层以提供额外的厚度并且盖住第一阻挡层以使激光平坦化期间由于第一阻挡层引起的气体发射和增强的光学消融最小化，并且在并在激光平面化后产生理想的表面形貌。第二层优选为Ti。在不破坏真空的情况下，在沉积第二阻挡层之后形成金属互连层。金属互连层优选为铝或其合金。铝层在互连金属的熔点之上在非常短的时间内退火以使铝平坦化并使铝流动以填充任何空隙。铝和阻挡层被蚀刻以形成适当的互连图案。

9. 发明授权

US5147819A Semiconductor metallization method 失效
标题翻译：半导体金属化方法
公开(公告)号：US5147819A
公开(公告)日：1992-09-15
申请号：US659866
申请日：1991-02-21
申请人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
发明人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
IPC分类号： H01L21/321 , H01L21/768
CPC分类号： H01L21/321 , H01L21/7684 , H01L21/76882 , Y10S148/02 , Y10S148/093
摘要： A method of applying an alloy layer of predetermined thickness on a semiconductor wafer to fill contact openings having a defined diameter, the method comprising the following steps:chemical vapor depositing (CVD) a layer of elemental metal atop the wafer to a thickness of from 5% to 35% of the defined contact diameter;sputtering a layer of an alloy atop the chemical vapor deposited layer of elemental metal to a thickness which results in the combination of the chemical vapor deposited and sputtered layers having substantially the predetermined overall layer thickness; andcombining and intermixing the sputtered alloy layer with the chemical vapor deposited elemental metal layer to form an overall homogenous alloy layer by applying energy to the sputtered alloy layer, the application of energy also filling contact openings and planarizing the homogenous layer.Preferably, the CVD layer has a thickness of from 10% to 20%, and the energy is applied by a scanning pulsed laser.
摘要翻译：一种在半导体晶片上施加预定厚度的合金层以填充具有限定直径的接触开口的方法，该方法包括以下步骤：在晶片顶部化学气相沉积（CVD）一层元素金属至5 定义的接触直径的百分之三十五; 在元素金属的化学气相沉积层的顶部溅射合金层，其厚度使得化学气相沉积和溅射层的组合具有基本上预定的总层厚度; 并将溅射的合金层与化学气相沉积的元素金属层组合和混合，以通过向溅射的合金层施加能量来形成整体均匀的合金层，施加能量也填充接触开口并使均匀层平坦化。优选地，CVD层具有10％至20％的厚度，并且通过扫描脉冲激光施加能量。

10. 发明授权

US08384192B2 Methods for forming small-scale capacitor structures 有权
标题翻译：形成小型电容器结构的方法
公开(公告)号：US08384192B2
公开(公告)日：2013-02-26
申请号：US13047430
申请日：2011-03-14
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与介电层接触并具有不大于约的厚度。

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