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    • 1. 发明申请
    • NON-VOLATILE MEMORY DEVICE
    • 非易失性存储器件
    • US20150318293A1
    • 2015-11-05
    • US14640784
    • 2015-03-06
    • Chang Hyun LEEJin-Kyu KIM
    • Chang Hyun LEEJin-Kyu KIM
    • H01L27/115
    • H01L27/11556H01L27/11524H01L27/11529H01L27/11541H01L27/11573
    • A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided.
    • 一种非易失性存储器件,包括连接到多个存储器单元的包括多个存储器单元和字线和位线的单元阵列区域,包括页缓冲器电路和行解码器电路的核心电路区域, 寻呼缓冲电路,被配置为临时存储输入到多个存储单元并从多个存储单元输出的数据;以及行解码器电路,被配置为选择与输入的地址对应的一些字线,以及包括数据输入的输入/输出电路区 /输出缓冲器电路,数据输入/输出缓冲电路被配置为发送数据到页缓冲器电路中的至少一个并从页缓冲器电路接收数据,并且输入/输出电路区域包括至少一个不对称晶体管,源极 区域和相对于栅极结构不对称地设置的漏极区域。