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1. 发明授权

US5465367A Slow memory refresh in a computer with a limited supply of power 失效
标题翻译：在电力供应有限的电脑中缓慢的内存刷新
公开(公告)号：US5465367A
公开(公告)日：1995-11-07
申请号：US277771
申请日：1994-07-19
申请人： Chandrashekar M. Reddy , Scott D. Hirose , Sung-Soo Cho , James P. Kardach , Steven M. Farrer , Meeling Roberts
发明人： Chandrashekar M. Reddy , Scott D. Hirose , Sung-Soo Cho , James P. Kardach , Steven M. Farrer , Meeling Roberts
IPC分类号： G06F1/04 , G06F1/32 , G06F15/78 , G11C11/401 , G11C11/406
CPC分类号： G06F1/3275 , G06F1/3203 , G11C11/406 , Y02B60/1228 , Y02B60/32
摘要： A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.
摘要翻译：电源暂停模式激活计算机系统中具有有限电源的缓慢的DRAM刷新。电源挂起模式减少了计算机系统消耗的功耗，同时保留了内存的内容。使用慢刷新时钟的DRAM的循环刷新大大降低了计算机暂停时消耗的功率。这种技术对于电池供电的便携式计算机系统特别有用。当外部或内部条件导致计算机系统转换到掉电模式时，IO子系统通知CPU，该CPU为IO子系统和视频子系统设置控制位。 IO子系统然后开始产生缓慢的DRAM刷新脉冲。一旦CPU和视频子系统检测到电源暂停模式激活，系统内存和视频存储器将使用缓慢的刷新时钟刷新。因此，刷新过程中消耗的功率大大降低。当IO子系统接收到恢复信号时，缓慢的刷新时钟被终止，系统存储器和视频存储器将使用正常的更快的时钟再次刷新。

2. 发明授权

US5422523A Apparatus for translating logic signal levels from 3.3 volts to 5 volts 失效
标题翻译：将逻辑信号电平从3.3伏特转换为5伏特的装置
公开(公告)号：US5422523A
公开(公告)日：1995-06-06
申请号：US125542
申请日：1993-09-22
申请人： Meeling Roberts , Ronald J. Mayer , Waleed S. Almulla , Bradley G. Heaney , Gloria Leong
发明人： Meeling Roberts , Ronald J. Mayer , Waleed S. Almulla , Bradley G. Heaney , Gloria Leong
IPC分类号： H03K19/0185 , H03K5/003
CPC分类号： H03K19/018521
摘要： An apparatus having a 3.3 volt power supply and a 5 volt power supply, wherein digital signals are processed on a 3.3 volt basis which are translated to a 5 volt basis by a voltage translation circuit before being output. The voltage translator is comprised of an inverter for inverting an input signal. The inverter is powered by the 3.3 volt power supply. A p-channel transistor having its source coupled to the 5 volt power supply and its gate driven by the output of the inverter is implemented. When the inverter generates a low logic, the p-channel transistor is turned on and outputs 5 volts. An n-channel transistor having its source coupled to ground and its gate driven by the output of the inverter is also implemented. When the output of the inverter is 3.3 volts, the n-channel transistor is turned on, which pulls the output to ground. Therefore, when the input signal is at 3.3 volts, a 5 volt signal is output from the voltage translation circuit. When the input signal is at 0 volts, the output signal is, likewise, at 0 volts.
摘要翻译：一种具有3.3伏电源和5伏电源的装置，其中数字信号以3.3伏为基准进行处理，在输出之前由电压转换电路转换为5伏特。电压转换器包括用于反相输入信号的反相器。变频器由3.3伏电源供电。实现了其源极耦合到5伏电源并且由逆变器的输出驱动的栅极的p沟道晶体管。当逆变器产生低逻辑时，p沟道晶体管导通，输出5伏特。还实现了其源极耦合到地并且由逆变器的输出驱动的栅极的n沟道晶体管。当变频器的输出为3.3V时，n沟道晶体管导通，将输出端接地。因此，当输入信号为3.3伏时，从电压转换电路输出5伏特信号。当输入信号为0伏时，输出信号同样为0伏。

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