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1. 发明授权

US08298846B2 Transparent conductor based pinned photodiode 有权
标题翻译：透明导体固定光电二极管
公开(公告)号：US08298846B2
公开(公告)日：2012-10-30
申请号：US12704769
申请日：2010-02-12
申请人： Chandra Mouli , Howard E. Rhodes
发明人： Chandra Mouli , Howard E. Rhodes
IPC分类号： H01L21/00
CPC分类号： H01L27/14609 , H01L27/14601 , H01L27/1463 , H01L27/14689
摘要： A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region in a semiconductor substrate. A gate conductor is formed on top of the gate oxide. The gate conductor is transparent, and in one embodiment is a layer of indium-tin oxide. The transparent conductor can be biased to reduce the need for a surface dopant in creating a pinned photodiode region. The biasing of the transparent conductor produces a hole-rich accumulation region near the surface of the substrate. The gate conductor material permits a greater amount of charges from short wavelength light to be captured in the photo-sensing region in the substrate, and thereby increases the quantum efficiency of the photosensor.
摘要翻译：具有改善的短波长光响应的钉扎光电二极管。在本发明的示例性实施例中，在半导体衬底中的掺杂的掩埋区域上形成栅极氧化物。栅极导体形成在栅极氧化物的顶部。栅极导体是透明的，在一个实施例中是一层氧化铟锡。透明导体可以被偏置以减少在产生钉扎光电二极管区域时对表面掺杂剂的需要。透明导体的偏压在基板的表面附近产生一个富含孔的堆积区域。栅极导体材料允许在衬底中的光敏区域中捕获较短波长的光的更大量的电荷，从而提高光电传感器的量子效率。

2. 发明授权

US07898010B2 Transparent conductor based pinned photodiode 有权
标题翻译：透明导体固定光电二极管
公开(公告)号：US07898010B2
公开(公告)日：2011-03-01
申请号：US10880646
申请日：2004-07-01
申请人： Chandra Mouli , Howard E. Rhodes
发明人： Chandra Mouli , Howard E. Rhodes
IPC分类号： H01L31/113
CPC分类号： H01L27/14609 , H01L27/14601 , H01L27/1463 , H01L27/14689
摘要： A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region in a semiconductor substrate. A conductor is formed on top of the gate oxide. The gate conductor is transparent, and in one embodiment is a layer of indium-tin oxide. The transparent conductor can be biased to reduce the need for a surface dopant in creating a pinned photodiode region. The biasing of the transparent conductor produces a hole-rich accumulation region near the surface of the substrate. The gate conductor material permits a greater amount of charges from short wavelength light to be captured in the photo-sensing region in the substrate, and thereby increases the quantum efficiency of the photosensor.
摘要翻译：具有改善的短波长光响应的钉扎光电二极管。在本发明的示例性实施例中，在半导体衬底中的掺杂的掩埋区域上形成栅极氧化物。导体形成在栅极氧化物的顶部。栅极导体是透明的，在一个实施例中是一层氧化铟锡。透明导体可以被偏置以减少在产生钉扎光电二极管区域时对表面掺杂剂的需要。透明导体的偏压在基板的表面附近产生一个富含孔的堆积区域。栅极导体材料允许在衬底中的光敏区域中捕获较短波长的光的更大量的电荷，从而提高光电传感器的量子效率。

3. 发明申请

US20090206429A1 ANGLED IMPLANT FOR TRENCH ISOLATION 有权
标题翻译： ANGED植入物进行分离
公开(公告)号：US20090206429A1
公开(公告)日：2009-08-20
申请号：US12400597
申请日：2009-03-09
申请人： Howard E. Rhodes , Chandra Mouli
发明人： Howard E. Rhodes , Chandra Mouli
IPC分类号： H01L29/06 , H01L31/02
CPC分类号： H01L21/26586 , H01L21/76224 , H01L27/1463 , H01L27/14643 , H01L27/14689
摘要： A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant and a 90 degree implant, of dopants of the first conductivity type. The sidewall and bottom implanted region located adjacent the trench isolation reduces surface leakage and dark current.
摘要翻译：公开了具有位于第一导电类型的衬底内的侧壁和底部注入区的沟槽隔离。侧壁和底部植入区域由第一导电类型的掺杂剂的成角度的植入物，90度植入物或倾斜植入物和90度植入物的组合形成。位于沟槽隔离附近的侧壁和底部注入区域减少了表面泄漏和暗电流。

4. 发明授权

US07573113B2 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation 有权
标题翻译：具有超浅结的光电二极管，用于高量子效率CMOS图像传感器和形成方法
公开(公告)号：US07573113B2
公开(公告)日：2009-08-11
申请号：US11093286
申请日：2005-03-30
申请人： Chandra Mouli , Howard E. Rhodes , Richard A. Mauritzson
发明人： Chandra Mouli , Howard E. Rhodes , Richard A. Mauritzson
IPC分类号： H01L27/148 , H01L29/80
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1463 , H01L27/14643 , H01L27/14689 , H01L31/0352 , H01L31/101
摘要： A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.
摘要翻译：公开了具有第一导电类型的超浅高掺杂表面层和形成方法的钉扎光电二极管。超浅高掺杂表面层的厚度为约100埃至约500埃，掺杂剂浓度为约5×10 17原子/ cm 3至约1×10 19原子/ cm 3。超浅高掺杂表面层通过将离子从掺杂层扩散到衬底中或通过等离子体掺杂工艺形成。超浅钉扎层与第二导电类型的电荷收集区域接触。

5. 发明授权

US07226803B2 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation 有权
标题翻译：具有超浅结的光电二极管，用于高量子效率CMOS图像传感器和形成方法
公开(公告)号：US07226803B2
公开(公告)日：2007-06-05
申请号：US11220670
申请日：2005-09-08
申请人： Chandra Mouli , Howard E. Rhodes , Richard A. Mauritzson
发明人： Chandra Mouli , Howard E. Rhodes , Richard A. Mauritzson
IPC分类号： H01L31/101
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1463 , H01L27/14643 , H01L27/14689 , H01L31/0352 , H01L31/101
摘要： A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.
摘要翻译：公开了具有第一导电类型的超浅高掺杂表面层和形成方法的钉扎光电二极管。超浅高掺杂表面层的厚度为约100埃至约500埃，掺杂剂浓度约5×10 17原子/ cm 3至约1×10 3原子/ SUP> 19个/ cm 3原子/ cm 3。超浅高掺杂表面层通过将离子从掺杂层扩散到衬底中或通过等离子体掺杂工艺形成。超浅钉扎层与第二导电类型的电荷收集区域接触。

6. 发明授权

US07138287B2 Reduced barrier photodiode/gate device structure for high efficiency charge transfer and reduced lag and method of formation 有权
标题翻译：降低栅极光电二极管/栅极器件结构，实现高效率电荷转移和滞后和形成方法
公开(公告)号：US07138287B2
公开(公告)日：2006-11-21
申请号：US10932287
申请日：2004-09-02
申请人： Chandra Mouli , Howard E. Rhodes
发明人： Chandra Mouli , Howard E. Rhodes
IPC分类号： H01L21/00
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L27/14643
摘要： A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.
摘要翻译：公开了一种在栅极和光电二极管彼此靠近的区域附近具有降低的势垒的像素单元及其形成方法。本发明的实施例提供了一种包括衬底的像素单元。晶体管的栅极至少部分地形成在衬底的表面下方，并且光电二极管与栅极相邻。光电二极管包括第一导电类型的掺杂表面层和位于掺杂表面层下面的第二导电类型的掺杂区域。掺杂表面层至少部分地高于栅极底部的电平。

7. 发明申请

US20100201859A1 Transparent Conductor Based Pinned Photodiode 有权
标题翻译：基于透明导体的固定光电二极管
公开(公告)号：US20100201859A1
公开(公告)日：2010-08-12
申请号：US12704769
申请日：2010-02-12
申请人： Chandra Mouli , Howard E. Rhodes
发明人： Chandra Mouli , Howard E. Rhodes
IPC分类号： H04N5/335 , H01L31/18
CPC分类号： H01L27/14609 , H01L27/14601 , H01L27/1463 , H01L27/14689
摘要： A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region in a semiconductor substrate. A gate conductor is formed on top of the gate oxide. The gate conductor is transparent, and in one embodiment is a layer of indium-tin oxide. The transparent conductor can be biased to reduce the need for a surface dopant in creating a pinned photodiode region. The biasing of the transparent conductor produces a hole-rich accumulation region near the surface of the substrate. The gate conductor material permits a greater amount of charges from short wavelength light to be captured in the photo-sensing region in the substrate, and thereby increases the quantum efficiency of the photosensor.
摘要翻译：具有改善的短波长光响应的钉扎光电二极管。在本发明的示例性实施例中，在半导体衬底中的掺杂的掩埋区域上形成栅极氧化物。栅极导体形成在栅极氧化物的顶部。栅极导体是透明的，在一个实施例中是一层氧化铟锡。透明导体可以被偏置以减少在产生钉扎光电二极管区域时对表面掺杂剂的需要。透明导体的偏压在基板的表面附近产生一个富含孔的堆积区域。栅极导体材料允许在衬底中的光敏区域中捕获较短波长的光的更大量的电荷，从而提高光电传感器的量子效率。

8. 发明授权

US07662658B2 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation 有权
标题翻译：具有超浅结的光电二极管，用于高量子效率CMOS图像传感器和形成方法
公开(公告)号：US07662658B2
公开(公告)日：2010-02-16
申请号：US11783040
申请日：2007-04-05
申请人： Chandra Mouli , Howard E. Rhodes , Richard A. Mauritzson
发明人： Chandra Mouli , Howard E. Rhodes , Richard A. Mauritzson
IPC分类号： H01L21/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1463 , H01L27/14643 , H01L27/14689 , H01L31/0352 , H01L31/101
摘要： A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface latter has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.
摘要翻译：公开了具有第一导电类型的超浅高掺杂表面层和形成方法的钉扎光电二极管。超浅高掺杂表面层的厚度为约100埃至约500埃，掺杂剂浓度为约5×10 17原子/ cm 3至约1×10 19原子/ cm 3。超浅高掺杂表面层通过将离子从掺杂层扩散到衬底中或通过等离子体掺杂工艺形成。超浅钉扎层与第二导电类型的电荷收集区域接触。

9. 发明授权

US07187018B2 Reduced barrier photodiode/transfer gate device structure of high efficiency charge transfer and reduced lag and method of formation 有权
标题翻译：降低栅极光电二极管/转移栅极器件结构的高效电荷转移和滞后及形成方法
公开(公告)号：US07187018B2
公开(公告)日：2007-03-06
申请号：US10602721
申请日：2003-06-25
申请人： Chandra Mouli , Howard E. Rhodes
发明人： Chandra Mouli , Howard E. Rhodes
IPC分类号： H01L29/74
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L27/14643
摘要： A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.
摘要翻译：公开了一种在栅极和光电二极管彼此靠近的区域附近具有降低的势垒的像素单元及其形成方法。本发明的实施例提供了一种包括衬底的像素单元。晶体管的栅极至少部分地形成在衬底的表面下方，并且光电二极管与栅极相邻。光电二极管包括第一导电类型的掺杂表面层和位于掺杂表面层下面的第二导电类型的掺杂区域。掺杂表面层至少部分地高于栅极底部的电平。

10. 发明授权

US07563631B2 Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduced lag and method of formation 有权
标题翻译：降低栅极光电二极管/栅极器件结构，实现高效率电荷转移和滞后和形成方法
公开(公告)号：US07563631B2
公开(公告)日：2009-07-21
申请号：US11582373
申请日：2006-10-18
申请人： Chandra Mouli , Howard E. Rhodes
发明人： Chandra Mouli , Howard E. Rhodes
IPC分类号： H01L21/00
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L27/14643
摘要： A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.
摘要翻译：公开了一种在栅极和光电二极管彼此靠近的区域附近具有降低的势垒的像素单元及其形成方法。本发明的实施例提供了一种包括衬底的像素单元。晶体管的栅极至少部分地形成在衬底的表面下方，并且光电二极管与栅极相邻。光电二极管包括第一导电类型的掺杂表面层和位于掺杂表面层下面的第二导电类型的掺杂区域。掺杂表面层至少部分地高于栅极底部的电平。

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