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1. 发明授权

US06247124B1 Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions 有权
标题翻译：使用指令行中的两步分支操作的第二操作的相对位置计算具有目标行索引的分支预测条目
公开(公告)号：US06247124B1
公开(公告)日：2001-06-12
申请号：US09363635
申请日：1999-07-30
申请人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
发明人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
IPC分类号： G06F932
CPC分类号： G06F9/3885 , G06F9/322 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3844
摘要： A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.
摘要翻译：计算系统包括具有存储多条指令的多行的指令存储器的装置，以及存储多个分支预测条目的分支存储器，每个分支预测条目包含用于预测分支指定的分支存储在指令存储器中的指令将在执行分支指令时进行。每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段，以及指示分支指令在与目标地址对应的行内位于何处的源字段。计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出，在包含分支指令的行后立即进入管道。无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。

2. 发明授权

US5954815A Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address 失效
标题翻译：在预测的两步分支操作与第二操作相对目标地址之间使获取的指令块中的指令无效
公开(公告)号：US5954815A
公开(公告)日：1999-09-21
申请号：US781851
申请日：1997-01-10
申请人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
发明人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/322 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3844
摘要： A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.
摘要翻译：一种计算系统，包括包括存储多条指令的多行的指令存储器和存储多个分支预测条目的分支存储器的装置，每个分支预测条目包含用于预测由a 当执行分支指令时，将采用存储在指令存储器中的分支指令。每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段，以及指示分支指令在与目标地址对应的行内位于何处的源字段。计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出，在包含分支指令的行后立即进入管道。无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。

3. 发明授权

US06691221B2 Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution 失效
标题翻译：在调度剩余插槽并行执行之前先加载先前在多个指令调度缓冲区中调度的插槽
公开(公告)号：US06691221B2
公开(公告)日：2004-02-10
申请号：US09863898
申请日：2001-05-24
申请人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
发明人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/322 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3844
摘要： A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit. A feedback path is also provided to reload an instruction not previously dispatched.
摘要翻译：计算系统具有第一和第二指令存储电路，每个指令存储电路存储用于并行输出的N个指令。耦合到第一指令存储电路的指令调度电路调度存储在第一指令存储电路中的L指令，其中L小于或等于N.一个指令加载电路，耦合到指令调度电路和第一和第二指令指令存储电路，在从第一指令存储电路发出L指令之后并且从第一指令存储电路调度进一步的指令之前，将来自第二指令存储电路的L指令加载到第一指令存储电路中。指令加载电路将来自第二指令存储电路的L指令加载到先前由从第一指令存储电路分派的L指令占据的位置。还提供反馈路径来重新加载先前未发送的指令。

4. 发明授权

US5604909A Apparatus for processing instructions in a computing system 失效
标题翻译：用于在计算系统中处理指令的装置
公开(公告)号：US5604909A
公开(公告)日：1997-02-18
申请号：US168744
申请日：1993-12-15
申请人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
发明人： Chandra Joshi , Paul Rodman , Peter Hsu , Monica R. Nofal
IPC分类号： G06F9/32 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3885 , G06F9/322 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3844
摘要： A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.
摘要翻译：计算系统具有第一和第二指令存储电路，每个指令存储电路存储用于并行输出的N个指令。耦合到第一指令存储电路的指令调度电路调度存储在第一指令存储电路中的L指令，其中L小于或等于N.一个指令加载电路，耦合到指令调度电路和第一和第二指令指令存储电路，在从第一指令存储电路发出L指令之后并且从第一指令存储电路调度进一步的指令之前，将来自第二指令存储电路的L指令加载到第一指令存储电路中。还提供了用于绕过第二指令存储电路的旁路电路。

5. 发明授权

US06278876B1 System and method for implementing terminal to terminal connections via a geosynchronous earth orbit satellite 失效
标题翻译：通过地球同步轨道卫星实现终端到终端连接的系统和方法
公开(公告)号：US06278876B1
公开(公告)日：2001-08-21
申请号：US09115098
申请日：1998-07-13
申请人： Chandra Joshi , Anthony Noerpel , Neeraj Tewari , Gerard Stelzer , David Roos , Chi-Jiun Su
发明人： Chandra Joshi , Anthony Noerpel , Neeraj Tewari , Gerard Stelzer , David Roos , Chi-Jiun Su
IPC分类号： H04Q720
CPC分类号： H04B7/2125 , H04B7/18517 , H04B7/18539 , H04B7/18543 , H04B7/18558 , H04B7/18567 , H04B7/18571 , H04B7/1858 , H04B7/18582 , H04B7/19 , H04B7/2041 , H04W28/14 , H04W52/0203 , H04W52/0216 , H04W72/0413 , H04W72/042 , H04W74/00 , H04W76/10 , H04W76/25 , H04W80/00 , H04W84/06 , Y02D70/1222 , Y02D70/164 , Y02D70/20 , Y02D70/446
摘要： A system and method for implementing single hop space segment terminal to terminal connections. The system includes a satellite-based radio frequency (RF) communication link for conveying multiple communication channels over the space segment via one or more spot beams. A terrestrial supervisory transceiver such as a gateway station is provided in communication with the satellite-based communication link. Mobile hand-held terminals (HHTs), herein first and second access terminals, may be located within one or more of the spot beams to communicate with one another via a single hop connection through a satellite of the system. A switch is provided for communication switching with the satellite of the system for the multiple communication channels to couple the first access terminal and the second access terminal over the space segment via one or more of the spot beams. The terrestrial supervisory transceiver or gateway is provided in communication with the satellite switch via the satellite-based communication link for implementing the single hop space segment terminal to terminal connection.
摘要翻译：一种实现单跳空间段终端到终端连接的系统和方法。该系统包括用于经由一个或多个点波束在空间段上传送多个通信信道的基于卫星的射频（RF）通信链路。提供与卫星通信链路通信的诸如网关站的地面监控收发器。本文中的第一和第二接入终端中的移动手持终端（HHT）可以位于一个或多个点波束内，以经由通过系统的卫星的单跳连接来彼此通信。提供了用于与用于多个通信信道的系统的卫星进行通信切换的开关，以通过一个或多个点波束将空间段上的第一接入终端和第二接入终端耦合。提供地面监控收发信机或网关，通过基于卫星的通信链路与卫星交换机通信，实现单跳空间段终端到终端连接。

6. 发明授权

US06289482B1 Error and flow control in a satellite communications system 失效
标题翻译：卫星通信系统中的误差和流量控制
公开(公告)号：US06289482B1
公开(公告)日：2001-09-11
申请号：US09115099
申请日：1998-07-13
申请人： Chandra Joshi , Anthony Noerpel , Xiaoping He , Prabir Datta
发明人： Chandra Joshi , Anthony Noerpel , Xiaoping He , Prabir Datta
IPC分类号： G08C2502
CPC分类号： H04B7/2125 , H04B7/18517 , H04B7/18539 , H04B7/18543 , H04B7/18558 , H04B7/18567 , H04B7/18571 , H04B7/1858 , H04B7/18582 , H04B7/19 , H04B7/2041 , H04W28/14 , H04W52/0203 , H04W52/0216 , H04W72/0413 , H04W72/042 , H04W74/00 , H04W76/10 , H04W76/25 , H04W80/00 , H04W84/06 , Y02D70/1222 , Y02D70/164 , Y02D70/20 , Y02D70/446
摘要： An approach for error flow control in a communications system involves receiving a plurality of frames of data; determining in said plurality of frames of data, two or more contiguous defective frames of data, the two or more contiguous defective frames of data being followed by at least one frame of data in said plurality of frames that is not defective; forming a group reject message indicative of a range of the two or more contiguous defective frames; transmitting the group reject message; and receiving replacement frames, the replacement frames corresponding to the two or more contiguous defective frames, wherein said at least one frame that is not defective is not received again in response to the group reject message.
摘要翻译：通信系统中的误差流控制方法包括：接收多个数据帧; 在所述多个数据帧中确定两个或更多个连续的缺陷数据帧，所述两个或更多个连续的缺陷数据帧之后是所述多个帧中的至少一帧数据，该数据帧不是有缺陷的; 形成指示所述两个或更多个连续缺陷帧的范围的组拒绝消息; 发送组拒绝消息; 以及接收替换帧，所述替换帧对应于所述两个或更多个连续的缺陷帧，其中，所述至少一个不具有缺陷的帧不响应于所述组拒绝消息被再次接收。

7. 发明授权

US06650895B1 In-call DTMF transport for geostationary mobile satellite communication system 有权
标题翻译：用于对地静止移动卫星通信系统的通话DTMF传输
公开(公告)号：US06650895B1
公开(公告)日：2003-11-18
申请号：US09447696
申请日：1999-11-23
申请人： Channasandra Ravishankar , David Roos , Anthony Noerpel , Chandra Joshi , James Hobza , Prabir Datta , Yi Chen
发明人： Channasandra Ravishankar , David Roos , Anthony Noerpel , Chandra Joshi , James Hobza , Prabir Datta , Yi Chen
IPC分类号： H04Q720
CPC分类号： H04B7/19 , H04M3/2281 , H04M3/533 , H04Q1/45
摘要： A system and a methodology to improve the end-user quality of service both in terms of response time and reliability for the transport of in-call DTMF signals in wireless systems, particularly in geostationary mobile satellite systems. The methodology encompasses several techniques to provide acceptable end-to-end quality of service for DTMF. A technique is applicable for transport of DTMF in the wireless subscriber to network direction, where DTMF digits are carried in the form of an out-band message. The central part of the technique is to allow multiple key presses in the same message, thereby increasing efficiency and throughput in long-delay environment. Another technique utilizes the vocoder's functionality to carry DTMF in-band, thereby reducing system complexity. The scheme makes the use of an integrated DTMF detector which can classify a given frame of signal into several classes so that the DTMF encoded packet can carry a unique pattern across the air-interface to the voice decoder at AT, which is capable of identifying the pattern. Another technique pertains to the use of a message based DTMF transport between two-ATs on a separate logical channel with a unique Service Access point Identifier (SAPI) providing guaranteed service for DTMF transport in an AT-AT call.
摘要翻译：在无线系统，特别是对地静止移动卫星系统中，在无线系统中传输呼叫中的DTMF信号的响应时间和可靠性方面，提高最终用户服务质量的系统和方法。该方法包括几种为DTMF提供可接受的端到端服务质量的技术。一种技术适用于将无线用户中的DTMF传输到网络方向，其中DTMF数字以带外消息的形式携带。该技术的核心部分是允许同一消息中的多个按键按压，从而在长时间延迟环境中提高效率和吞吐量。另一种技术利用声码器的功能来携带DTMF带内，从而降低系统的复杂性。该方案使用集成的DTMF检测器，其可以将给定的信号帧分类成多个等级，使得DTMF编码的分组可以在AT的语音解码器的空中接口上携带唯一的模式，其能够识别模式。另一种技术涉及在独立的逻辑信道上的两个AT之间使用基于消息的DTMF传输与唯一的服务接入点标识符（SAPI），其在AT-AT呼叫中为DTMF传输提供有保证的服务。

8. 发明授权

US06249677B1 Apparatus and method for delivering key information of a channel request message from a user terminal to a network 有权
标题翻译：一种从用户终端向网络传送信道请求消息的密钥信息的装置和方法
公开(公告)号：US06249677B1
公开(公告)日：2001-06-19
申请号：US09247849
申请日：1999-02-11
申请人： Anthony Noerpel , Chandra Joshi , Stephanie Demers
发明人： Anthony Noerpel , Chandra Joshi , Stephanie Demers
IPC分类号： H04Q720
CPC分类号： H04B7/18558 , H04B7/2125
摘要： An apparatus and method, for use with the satellite-based communications network, for improving the reliability and speed at which communication between a user terminal and the network is established. The apparatus and method arranges data of a channel request message transmitted from a user terminal to a satellite in the satellite-based network to insure that the most critical data for establishing communication between the user terminal and the satellite-based network is received at the satellite during the appropriate receiving time frame window. The channel request message includes a first data group necessary for establishing a communication link for which information is transmitted between the apparatus and the network, and a second data group including information for decreasing the amount time necessary to establish the communication link. The first data group is positioned at the center of the channel request message, with portions of the second data group at opposite ends of the channel request message. The time at which the user terminal transmits the channel request message is set based on a location of the apparatus within a spot beam, to take into account the appropriate propagation delay time for the message to travel from the apparatus to the satellite in the network, thus assuring that at least the first data group of the channel request message is received at the satellite during an appropriate receiving time frame window.
摘要翻译：一种用于卫星通信网络的设备和方法，用于提高用户终端和网络之间的通信建立的可靠性和速度。该装置和方法将从用户终端发送的信道请求消息的数据排列到基于卫星的网络中的卫星，以确保在卫星接收用于建立用户终端和基于卫星的网络之间的通信的最关键数据在适当的接收时间窗口。信道请求消息包括建立用于在装置和网络之间传送信息的通信链路所需的第一数据组，以及包括用于减少建立通信链路所需的时间量的信息的第二数据组。第一数据组位于信道请求消息的中心，第二数据组的部分位于信道请求消息的相对端。用户终端发送信道请求消息的时间是基于点光束内的设备的位置来设置的，以考虑消息从设备行进到网络中的卫星的适当的传播延迟时间，从而确保在适当的接收时间窗口期间至少在卫星处接收信道请求消息的第一数据组。

9. 发明申请

US20150113221A1 HYBRID INPUT/OUTPUT WRITE OPERATIONS 审中-公开
标题翻译：混合输入/输出写操作
公开(公告)号：US20150113221A1
公开(公告)日：2015-04-23
申请号：US13997426
申请日：2013-03-15
申请人： Herbert Hum , Chandra Joshi , Rahul Pal , Luke Chang
发明人： Herbert Hum , Chandra Joshi , Rahul Pal , Luke Chang
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F12/0875 , G06F2212/225 , G06F2212/452 , Y02D10/13
摘要： A first processor receives a write request from an input/output (I/O) device connected to the first processor. The first processor determines whether the write request satisfies an allocating write criterion. Responsive to determining that the write request satisfies the allocating write criterion, the first processor writes data associated with the write request to a cache of the first processor.
摘要翻译：第一处理器从连接到第一处理器的输入/输出（I / O）设备接收写请求。第一处理器确定写入请求是否满足分配写入标准。响应于确定写请求满足分配写标准，第一处理器将与写请求相关联的数据写入第一处理器的高速缓存。

10. 发明申请

US20050226160A1 Method and system for multi-PHY addressing 有权
标题翻译：多PHY寻址方法和系统
公开(公告)号：US20050226160A1
公开(公告)日：2005-10-13
申请号：US11144257
申请日：2005-06-03
申请人： Jay Sethuram , Richard Weber , Chandra Joshi
发明人： Jay Sethuram , Richard Weber , Chandra Joshi
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/06 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/56 , H04L12/66
CPC分类号： H04L12/5601 , H04L49/405
摘要： Multi-PHY addressing from source to destination in which n-number of channels or ports are used in a PHY layer device for communication with a link layer device. A single link layer to a single-PHY layer topology and a single link layer to a multi-PHY layer topology comprising multiple ports or channels receives a plurality of channels groups. Status indication signal is provided on continuous basis for the direct status for up to a predetermined number of channels.
摘要翻译：从源到目的地的多PHY寻址，其中在PHY层设备中使用n个信道或端口用于与链路层设备通信。包括多个端口或信道的单个PHY层拓扑和单个链路层到包含多个端口或信道的多PHY层拓扑的单个链路层接收多个信道组。连续地提供状态指示信号，用于直到预定数量的通道的直接状态。

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