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1. 发明申请

US20130148429A1 MEMORY DEVICE, METHOD OF PERFORMING READ OR WRITE OPERATION AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：存储器件，执行读或写操作的方法和包括其的存储器系统
公开(公告)号：US20130148429A1
公开(公告)日：2013-06-13
申请号：US13705143
申请日：2012-12-04
申请人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
发明人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
IPC分类号： G11C7/06 , G11C11/16 , G11C16/26 , G11C13/00
CPC分类号： G11C7/06 , G11C7/065 , G11C7/222 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/26 , G11C16/28 , G11C27/02 , G11C2207/002 , G11C2207/005 , G11C2213/71 , H01L27/222 , H01L43/08 , H01L45/04 , H01L45/06
摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.
摘要翻译：提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。第二开关被配置为接收第二CSL信号。感测和锁存电路（SLC）耦合在第一和第二开关之间。并且至少一个存储器单元耦合到第二开关。第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。还提供了使用这种存储器件执行读和写操作的方法。

2. 发明授权

US09171589B2 Memory device, method of performing read or write operation and memory system including the same 有权
标题翻译：存储器件，执行读或写操作的方法和包括其的存储器系统
公开(公告)号：US09171589B2
公开(公告)日：2015-10-27
申请号：US13705143
申请日：2012-12-04
申请人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
发明人： Chan-Kyung Kim , Yun-Sang Lee , Chul-Woo Park , Hong-Sun Hwang
IPC分类号： G11C16/04 , G11C7/06 , G11C13/00 , G11C11/16 , G11C16/26
CPC分类号： G11C7/06 , G11C7/065 , G11C7/222 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/26 , G11C16/28 , G11C27/02 , G11C2207/002 , G11C2207/005 , G11C2213/71 , H01L27/222 , H01L43/08 , H01L45/04 , H01L45/06
摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.
摘要翻译：提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。第二开关被配置为接收第二CSL信号。感测和锁存电路（SLC）耦合在第一和第二开关之间。并且至少一个存储器单元耦合到第二开关。第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。还提供了使用这种存储器件执行读和写操作的方法。

3. 发明授权

US08654595B2 Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters 有权
标题翻译：具有用于补偿存储单元参数变化的钳位电压产生电路的非易失性存储器件
公开(公告)号：US08654595B2
公开(公告)日：2014-02-18
申请号：US13604688
申请日：2012-09-06
申请人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
发明人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/12 , G11C11/1673
摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
摘要翻译：非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

4. 发明授权

US09183910B2 Semiconductor memory devices for alternately selecting bit lines 有权
标题翻译：用于交替选择位线的半导体存储器件
公开(公告)号：US09183910B2
公开(公告)日：2015-11-10
申请号：US13907223
申请日：2013-05-31
申请人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
发明人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
IPC分类号： G11C11/16 , G11C7/12
CPC分类号： G11C11/1653 , G11C7/12 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/1697
摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).
摘要翻译：半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和对多个STT-MRAM单元进行写入操作。该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号）。

5. 发明授权

US09330743B2 Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same 有权
标题翻译：电阻型存储器件的存储器核心，电阻型存储器件以及感测数据的方法
公开(公告)号：US09330743B2
公开(公告)日：2016-05-03
申请号：US14677991
申请日：2015-04-03
申请人： Chan-Kyung Kim , Kee-Won Kwon , Su-A Kim , Chul-Woo Park , Jae-Youn Youn
发明人： Chan-Kyung Kim , Kee-Won Kwon , Su-A Kim , Chul-Woo Park , Jae-Youn Youn
IPC分类号： G11C11/00 , G11C11/16 , G11C5/08 , G11C7/06 , G11C5/02 , G11C13/00 , G11C11/4091
CPC分类号： G11C11/16 , G11C5/025 , G11C5/08 , G11C7/065 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C13/0023 , G11C13/004 , G11C2013/0042 , G11C2213/79 , G11C2213/82
摘要： A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.
摘要翻译：电阻型存储器件的存储核心至少包括耦合到位线的第一电阻型存储单元，第一电阻转换器和位线读出放大器。第一电阻转换器在第一节点处耦合到位线。第一电阻转换器基于读列选择信号将第一电阻型存储单元的电阻转换成相应的电压。位线读出放大器耦合到第一节点处的位线，并且耦合到第二节点处的互补位线。位线检测放大器响应于感测控制信号而感测和放大位线和互补位线的电压差。

6. 发明申请

US20180189219A1 METHOD OF RECONFIGURING DQ PADS OF MEMORY DEVICE AND DQ PAD RECONFIGURABLE MEMORY DEVICE 审中-公开
公开(公告)号：US20180189219A1
公开(公告)日：2018-07-05
申请号：US15677475
申请日：2017-08-15
申请人： Chan-Kyung Kim
发明人： Chan-Kyung Kim
IPC分类号： G06F13/40 , G06F13/12 , G06F3/00
CPC分类号： G06F13/4095 , G06F3/002 , G06F13/12
摘要： A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.

7. 发明申请

US20050001670A1 Temperature sensing circuit and method 有权
标题翻译：温度检测电路及方法
公开(公告)号：US20050001670A1
公开(公告)日：2005-01-06
申请号：US10884684
申请日：2004-07-02
申请人： Kwang-hyun Kim , Chan-Kyung Kim
发明人： Kwang-hyun Kim , Chan-Kyung Kim
IPC分类号： G01K7/00 , G01K7/01 , H01L21/66 , H03K17/08 , H03K3/42
CPC分类号： G01K7/01 , H03K2017/0806
摘要： A temperature sensing circuit and method are provided. An example temperature sensing circuit includes a temperature sensing unit that outputs a temperature signal indicating whether the temperature in the semiconductor device is higher or lower than a reference temperature in response to a first current control signal or a second current control signal by using a first current level that is increased when the temperature rises and a second current level that is reduced when the temperature rises. The temperature sensing unit also includes a storage unit that stores and outputs the temperature signal, and a controller that changes the first current level or the second current level in response to the temperature signal output from the storage unit and generates the first current control signal or the second current control signal used to control the reference temperature.
摘要翻译：提供了温度检测电路和方法。一个示例性温度感测电路包括温度感测单元，其通过使用第一电流输出指示半导体器件中的温度是响应于第一电流控制信号还是第二电流控制信号而高于或低于参考温度的温度信号当温度升高时增加的电平和当温度升高时降低的第二电流水平。温度检测单元还包括存储并输出温度信号的存储单元，以及响应于从存储单元输出的温度信号而改变第一电流电平或第二电流电平的控制器，并且产生第一电流控制信号或用于控制参考温度的第二电流控制信号。

8. 发明授权

US07143303B2 Memory device for compensating for a clock skew causing a centering error and a method for compensating for the clock skew 失效
标题翻译：用于补偿引起定心误差的时钟偏移的存储器件和用于补偿时钟偏移的方法
公开(公告)号：US07143303B2
公开(公告)日：2006-11-28
申请号：US10804530
申请日：2004-03-19
申请人： Young-Soo Sohn , Chan-Kyung Kim
发明人： Young-Soo Sohn , Chan-Kyung Kim
IPC分类号： G06F1/04
CPC分类号： G11C29/028 , G06F1/10 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/50012
摘要： The present invention comprises a memory device for compensating for a clock skew that generates a centering error, and a method of compensating for the clock skew. To compensate for a clock skew that causes a centering error between an external clock signal and an output data signal, the memory device includes a phase detector (PD) and an up-down counter. The PD detects a phase difference between the output data signal and the external clock signal and generates an up signal or a down signal depending on the detected phase difference. The up-down counter is enabled by a calibration signal that directs a compensation of the skew and generates an offset code in response to the up signal or the down signal. The offset code is fed back to a delay locked loop (DLL) circuit and aligns the middle points of the output data signal with the edges of the external clock signal.
摘要翻译：本发明包括用于补偿产生定心误差的时钟偏差的存储器件以及补偿时钟偏移的方法。为了补偿引起外部时钟信号和输出数据信号之间的定心误差的时钟偏移，存储器件包括相位检测器（PD）和升降计数器。 PD检测输出数据信号和外部时钟信号之间的相位差，并根据检测到的相位差产生上行信号或下降信号。升降计数器通过校准信号启用，该校准信号指导偏斜的补偿，并响应于向上信号或下降信号产生偏移代码。偏移码反馈到延迟锁定环路（DLL）电路，并将输出数据信号的中点与外部时钟信号的边沿对齐。

9. 发明授权

US07078955B2 Temperature sensing circuit and method 有权
标题翻译：温度检测电路及方法
公开(公告)号：US07078955B2
公开(公告)日：2006-07-18
申请号：US10884684
申请日：2004-07-02
申请人： Kwang-hyun Kim , Chan-Kyung Kim
发明人： Kwang-hyun Kim , Chan-Kyung Kim
IPC分类号： H01L35/00
CPC分类号： G01K7/01 , H03K2017/0806
摘要： A temperature sensing circuit and method are provided. An example temperature sensing circuit includes a temperature sensing unit that outputs a temperature signal indicating whether the temperature in the semiconductor device is higher or lower than a reference temperature in response to a first current control signal or a second current control signal by using a first current level that is increased when the temperature rises and a second current level that is reduced when the temperature rises. The temperature sensing unit also includes a storage unit that stores and outputs the temperature signal, and a controller that changes the first current level or the second current level in response to the temperature signal output from the storage unit and generates the first current control signal or the second current control signal used to control the reference temperature.
摘要翻译：提供了温度检测电路和方法。一个示例性温度感测电路包括温度感测单元，其通过使用第一电流输出指示半导体器件中的温度是响应于第一电流控制信号还是第二电流控制信号而高于或低于参考温度的温度信号当温度升高时增加的电平和当温度升高时降低的第二电流水平。温度检测单元还包括存储并输出温度信号的存储单元，以及响应于从存储单元输出的温度信号而改变第一电流电平或第二电流电平的控制器，并且产生第一电流控制信号或用于控制参考温度的第二电流控制信号。

10. 发明申请

US20060071687A1 Output driver circuit with pre-emphasis function 失效
标题翻译：输出驱动电路具有预加重功能
公开(公告)号：US20060071687A1
公开(公告)日：2006-04-06
申请号：US11129469
申请日：2005-05-13
申请人： Chan-Kyung Kim
发明人： Chan-Kyung Kim
IPC分类号： H03K19/0175
CPC分类号： H04L25/0272
摘要： In an output driver circuit and method, a control circuit generates a control signal in response to a current internal data signal. An output driver generates an output data signal in response to the control signal. A pre-emphasis circuit adjusts a current flowing through a node having the control signal generated thereon in response to a previous internal data signal. The pre-emphasis circuit may also adjust the output signal in response to the previous internal data signal.
摘要翻译：在输出驱动器电路和方法中，控制电路响应于当前的内部数据信号产生控制信号。输出驱动器响应于控制信号产生输出数据信号。预加重电路响应于先前的内部数据信号来调节流过具有其上产生的控制信号的节点的电流。预加重电路还可以响应于先前的内部数据信号来调整输出信号。

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